公开(公告)号：US10936418B2

公开(公告)日：2021-03-02

申请号：US16444480

申请日：2019-06-18

Applicant: Intel Corporation

Inventor： Kiran Pangal ,  Prashant S. Damle ,  Rajesh Sundaram ,  Shekoufeh Qawami ,  Julie M. Walker ,  Doyle Rivers

IPC: G11C29/00 ,  G06F11/10 ,  H03M13/05 ,  H03M13/27 ,  H03M13/00 ,  G06F3/06 ,  H03M13/15 ,  H03M13/19

Abstract: Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.

公开(公告)号：US10310989B2

公开(公告)日：2019-06-04

申请号：US15721379

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Philip Hillier ,  Jeffrey W. Ryden ,  Muthukumar P. Swaminathan ,  Zion S. Kwok ,  Kunal A. Khochare ,  Richard P. Mangold ,  Prashant S. Damle

IPC: G06F12/126 ,  G06F12/02 ,  G11C7/22

Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller memory; a timestamp circuitry and a demarcation voltage (VDM) selection circuitry. The timestamp circuitry is to capture a current timer index from a timer circuitry in response to an initiation of a periodic patrol scrub and to compare the current timer index to a stored timestamp. The VDM selection circuitry is to update a state of a sub-block of a memory array, if the state is less than a threshold and a difference between the current timer index and the stored timestamp is nonzero. The timestamp circuitry is further to store the current timer index as a new timestamp.

公开(公告)号：US12230346B2

公开(公告)日：2025-02-18

申请号：US17358421

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Hemant P. Rao ,  Raymond W. Zeng ,  Prashant S. Damle ,  Zion S. Kwok ,  Kiran Pangal ,  Mase J. Taub

IPC: G11C29/00 ,  G11C7/06 ,  G11C29/12 ,  G11C29/42 ,  G11C29/44 ,  G11C29/50

Abstract: A read technique for both SLC (single level cell) and MLC (multi-level cell) cross-point memory can mitigate drift-related errors with minimal or no drift tracking. In one example, a read at a higher magnitude voltage is applied first, which causes the drift for cells in a lower threshold voltage state to be reset. In one example, the read at the first voltage can be a full float read to minimize disturb. A second read can then be performed at a lower voltage without the need to adjust the read voltage due to drift.

公开(公告)号：US10153015B2

公开(公告)日：2018-12-11

申请号：US15703589

申请日：2017-09-13

Applicant: Intel Corporation

Inventor： Prashant S. Damle ,  Frank T. Hady ,  Paul D. Ruby ,  Kiran Pangal ,  Sowmiya Jayachandran

IPC: G11C7/10 ,  G11C11/406 ,  G11C16/34

Abstract: In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells.

公开(公告)号：US20160284399A1

公开(公告)日：2016-09-29

申请号：US14671972

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Davide Mantegazza ,  Prashant S. Damle ,  Kiran Pangal ,  Hanmant P. Belgal ,  Abhinav Pandey

IPC: G11C13/00 ,  G11C11/56

CPC classification number: G11C13/004 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0033 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0052 ,  G11C2013/0057 ,  G11C2013/0083

Abstract: An apparatus is provided which comprises: a plurality of memory cells; a bias logic coupled with at least one memory cell of the plurality, the bias logic to: apply a first read voltage to the at least one memory cell; and apply a second read voltage to the at least one memory cell, the first read voltage being higher than the second read voltage; and a first circuit operable to float a word-line coupled to the at least one memory cell before the bias logic applies the first read voltage to the at least one memory cell. A method is provided which comprises: performing a first read operation to at least one memory cell; and performing a second read operation to the at least one memory cell after the first read operation completes, wherein the second read operation is different from the first read operation.

Abstract translation: 提供了一种装置，包括：多个存储单元; 偏置逻辑与所述多个存储单元中的至少一个存储单元耦合，所述偏置逻辑用于：将第一读取电压施加到所述至少一个存储单元; 并且向所述至少一个存储单元施加第二读取电压，所述第一读取电压高于所述第二读取电压; 以及第一电路，其可操作以在所述偏置逻辑将所述第一读取电压施加到所述至少一个存储器单元之前，浮动耦合到所述至少一个存储器单元的字线。 提供了一种方法，其包括：对至少一个存储单元执行第一读取操作; 以及在所述第一读取操作完成之后对所述至少一个存储器单元执行第二读取操作，其中所述第二读取操作与所述第一读取操作不同。

公开(公告)号：US09384801B2

公开(公告)日：2016-07-05

申请号：US14461154

申请日：2014-08-15

Applicant: INTEL CORPORATION

Inventor： Abhinav Pandey ,  Hanmant P. Belgal ,  Prashant S. Damle ,  Arjun Kripanidhi ,  Sebastian T. Uribe ,  Dany-Sebastien Ly-Gagnon ,  Sanjay Rangan ,  Kiran Pangal

IPC: G11C7/00 ,  G11C7/12 ,  G11C29/50 ,  G06F11/10 ,  G11C14/00 ,  G11C7/04 ,  G11C13/00

CPC classification number: G11C7/12 ,  G06F11/1072 ,  G11C7/04 ,  G11C11/5678 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0033 ,  G11C13/0069 ,  G11C14/0045 ,  G11C29/028 ,  G11C29/50004 ,  G11C2013/0057 ,  G11C2029/5004

Abstract: Embodiments including systems, methods, and apparatuses associated with expanding a threshold voltage window of memory cells are described herein. Specifically, in some embodiments memory cells may be configured to store data by being set to a set state or a reset state. In some embodiments, a dummy-read process may be performed on memory cells in the set state prior to a read process. In some embodiments, a modified reset algorithm may be performed on memory cells in the reset state. Other embodiments may be described or claimed.

Abstract translation: 这里描述包括与扩展存储器单元的阈值电压窗口相关联的系统，方法和装置的实施例。 具体地，在一些实施例中，存储器单元可以被配置为通过被设置为设置状态或复位状态来存储数据。 在一些实施例中，可以在读取处理之前在设置状态下对存储器单元执行伪读取处理。 在一些实施例中，可以在复位状态的存储器单元上执行修改的复位算法。 可以描述或要求保护其他实施例。

公开(公告)号：US20150309926A1

公开(公告)日：2015-10-29

申请号：US14705195

申请日：2015-05-06

Applicant: Intel Corporation

Inventor： Prashant S. Damle ,  Robert W. Faber ,  Ningde Xie

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7211

Abstract: Systems and methods of memory cell wear management that can achieve a more uniform distribution of write cycles across a memory cell address space. The systems and methods allow physical addresses of memory cells subjected to a high number of write cycles to be swapped with physical addresses of memory cells subjected to a lower number of write cycles. The physical address of a group of memory cells is a “hot address” if the write cycle count for that memory cell group exceeds a specified threshold. If the write cycle count for a group of memory cells does not exceed the specified threshold, then the physical address of that memory cell group is a “cold address”. The systems and methods allow the specified threshold of write cycle counts to be dynamically incremented to assure that cold addresses are available for swapping with hot addresses in the memory cell address space.

Abstract translation: 可以实现跨存储器单元地址空间的写周期更均匀分布的存储器单元磨损管理的系统和方法。 这些系统和方法允许经受大量写入周期的存储器单元的物理地址与经受较少写入周期的存储器单元的物理地址交换。 如果该存储单元组的写周期计数超过指定的阈值，则一组存储单元的物理地址是“热地址”。 如果一组存储单元的写周期计数不超过指定的阈值，则该存储单元组的物理地址为“冷地址”。 系统和方法允许指定的写周期计数阈值动态增加，以确保冷地址可用于与存储单元地址空间中的热地址进行交换。

公开(公告)号：US09136873B2

公开(公告)日：2015-09-15

申请号：US13792597

申请日：2013-03-11

Applicant: Intel Corporation

Inventor： Kiran Pangal ,  Prashant S. Damle ,  Rajesh Sundaram ,  Shekoufeh Qawami ,  Julie M. Walker ,  Doyle Rivers

IPC: H03M13/00 ,  H03M13/05 ,  H03M13/27 ,  G06F11/10 ,  H03M13/15 ,  H03M13/19

CPC classification number: G06F11/1076 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  H03M13/05 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/19 ,  H03M13/27 ,  H03M13/6508

Abstract: Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.

Abstract translation: 可以通过确定一组存储器阵列的逻辑阵列地址并且至少部分地基于该组内的至少两个存储器阵列的逻辑位置将逻辑阵列地址变换为至少两个唯一阵列地址来减少不可校正的存储器错误 的存储器阵列。 然后使用至少两个唯一的阵列地址分别访问至少两个存储器阵列。

公开(公告)号：US09032137B2

公开(公告)日：2015-05-12

申请号：US13682885

申请日：2012-11-21

Applicant: Intel Corporation

Inventor： Prashant S. Damle ,  Robert W. Faber ,  Ningde Xie

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7211

Abstract: Systems and methods of memory cell wear management that can achieve a more uniform distribution of write cycles across a memory cell address space. The systems and methods allow physical addresses of memory cells subjected to a high number of write cycles to be swapped with physical addresses of memory cells subjected to a lower number of write cycles. The physical address of a group of memory cells is a “hot address” if the write cycle count for that memory cell group exceeds a specified threshold. If the write cycle count for a group of memory cells does not exceed the specified threshold, then the physical address of that memory cell group is a “cold address”. The systems and methods allow the specified threshold of write cycle counts to be dynamically incremented to assure that cold addresses are available for swapping with hot addresses in the memory cell address space.

Abstract translation: 可以实现跨存储器单元地址空间的写周期更均匀分布的存储器单元磨损管理的系统和方法。 这些系统和方法允许经受大量写入周期的存储器单元的物理地址与经受较少写入周期的存储器单元的物理地址交换。 如果该存储单元组的写周期计数超过指定的阈值，则一组存储单元的物理地址是“热地址”。 如果一组存储单元的写周期计数不超过指定的阈值，则该存储单元组的物理地址为“冷地址”。 系统和方法允许指定的写周期计数阈值动态增加，以确保冷地址可用于与存储单元地址空间中的热地址进行交换。

公开(公告)号：US10679698B2

公开(公告)日：2020-06-09

申请号：US15939026

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Prashant S. Damle ,  Wei Fang ,  Albert Fazio

IPC: G11C11/00 ,  G11C13/00 ,  G06F13/40 ,  G06F13/16 ,  G11C29/02 ,  G11C29/50 ,  G11C29/52 ,  G11C29/44 ,  G11C29/04

Abstract: A memory device includes a memory array having multiple nonvolatile memory cells that stores data as a set or a reset state of the memory cells. The nonvolatile memory cells can be resistance-based memory, which stores data based on resistive state of the memory cells. A controller coupled to the memory array periodically samples set and reset margins for memory cells of the memory array. Responsive to detection of a change in a margin, the system can adaptively adjust a preset electrical setting used to differentiate between a set state and a reset state.