公开(公告)号：US20240258183A1

公开(公告)日：2024-08-01

申请号：US18632047

申请日：2024-04-10

Applicant: Intel Corporation

Inventor： Edvin CETEGEN ,  Jacob VEHONSKY ,  Nicholas S. HAEHN ,  Thomas HEATON ,  Steve S. CHO ,  Rahul JAIN ,  Tarek IBRAHIM ,  Antariksh Rao Pratap SINGH ,  Nicholas NEAL ,  Sergio CHAN ARGUEDAS ,  Vipul MEHTA

IPC: H01L23/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/16 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2924/18161

Abstract: Embodiments disclosed herein include electronic packages with underfill flow control features. In an embodiment, an electronic package comprises a package substrate and a plurality of interconnects on the package substrate. In an embodiment, a die is coupled to the package substrate by the plurality of interconnects and a flow control feature is adjacent on the package substrate. In an embodiment, the flow control feature is electrically isolated from circuitry of the electronic package. In an embodiment, the electronic package further comprises an underfill surrounding the plurality of interconnects and in contact with the flow control feature.

公开(公告)号：US20240105476A1

公开(公告)日：2024-03-28

申请号：US17951114

申请日：2022-09-23

Applicant: Intel Corporation

Inventor： Whitney BRYKS ,  Thomas HEATON ,  Joshua STACEY ,  Dilan SENEVIRATNE ,  Cansu ERGENE

IPC: B05C13/02 ,  B05C5/02 ,  B05D1/26

CPC classification number: B05C13/02 ,  B05C5/02 ,  B05D1/26

Abstract: The present disclosure is directed to a coating module including: a coating stage and a plurality of vertical guides configured to perpendicularly extend from the coating stage; a vertical movement mechanism configured to lower a framed panel along the plurality of vertical guides onto the coating stage; an optical alignment tool configured to provide feedback on a lateral alignment between an edge of the coating stage and the framed panel; and a dispensing unit configured to coat a surface of the panel.

公开(公告)号：US20240173953A1

公开(公告)日：2024-05-30

申请号：US18059993

申请日：2022-11-30

Applicant: Intel Corporation

Inventor： Joshua STACEY ,  Thomas HEATON ,  Dilan SENEVIRATNE

IPC: B32B37/00 ,  B32B37/02 ,  B32B37/06 ,  B32B37/20 ,  B32B37/30

CPC classification number: B32B37/0007 ,  B32B37/02 ,  B32B37/065 ,  B32B37/20 ,  B32B37/30 ,  B32B2038/0076

Abstract: The present disclosure is directed to an apparatus including a first laminating component configured to laminate a dry film onto a substrate using heat, and a focused cure module configured to selectively cure a first portion of the dry film without curing a second portion of the dry film. The first portion forms a perimeter that surrounds the second portion.

公开(公告)号：US20210082852A1

公开(公告)日：2021-03-18

申请号：US16572354

申请日：2019-09-16

Applicant: Intel Corporation

Inventor： Bradon C. MARIN ,  Jung Kyu HAN ,  Thomas HEATON ,  Ali LEHAF ,  Rahul MANEPALLI ,  Srinivas PIETAMBARAM ,  Jacob VEHONSKY

IPC: H01L23/00 ,  C25D3/38 ,  C25D7/12 ,  C25D5/02

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to manufacturing a package having a substrate with a first side and a second side opposite the first side, where a copper layer is coupled with a first region of the first side of the substrate and includes a plurality of bumps coupled with the first region of the first side of the substrate where one or more second regions on the first side of the substrate not coupled with a copper layer, and where a layout of the one or more second regions on the first side of the substrate is to vary a growth, respectively, of each of the plurality of bumps during a plating process by modifying a local copper density of each of the plurality of bumps.

公开(公告)号：US20250112136A1

公开(公告)日：2025-04-03

申请号：US18374937

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Bohan SHAN ,  Jesse JONES ,  Zhixin XIE ,  Bai NIE ,  Shaojiang CHEN ,  Joshua STACEY ,  Mitchell PAGE ,  Brandon C. MARIN ,  Jeremy D. ECTON ,  Nicholas S. HAEHN ,  Astitva TRIPATHI ,  Yuqin LI ,  Edvin CETEGEN ,  Jason M. GAMBA ,  Jacob VEHONSKY ,  Jianyong MO ,  Makoyi WATSON ,  Shripad GOKHALE ,  Mine KAYA ,  Kartik SRINIVASAN ,  Haobo CHEN ,  Ziyin LIN ,  Kyle ARRINGTON ,  Jose WAIMIN ,  Ryan CARRAZZONE ,  Hongxia FENG ,  Srinivas Venkata Ramanuja PIETAMBARAM ,  Gang DUAN ,  Dingying David XU ,  Hiroki TANAKA ,  Ashay DANI ,  Praveen SREERAMAGIRI ,  Yi LI ,  Ibrahim EL KHATIB ,  Aaron GARELICK ,  Robin MCREE ,  Hassan AJAMI ,  Yekan WANG ,  Andrew JIMENEZ ,  Jung Kyu HAN ,  Hanyu SONG ,  Yonggang Yong LI ,  Mahdi MOHAMMADIGHALENI ,  Whitney BRYKS ,  Shuqi LAI ,  Jieying KONG ,  Thomas HEATON ,  Dilan SENEVIRATNE ,  Yiqun BAI ,  Bin MU ,  Mohit GUPTA ,  Xiaoying GUO

IPC: H01L23/498 ,  H01L23/15

Abstract: Embodiments disclosed herein include apparatuses with glass core package substrates. In an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface. A sidewall is between the first surface and the second surface, and the substrate comprises a glass layer. In an embodiment, a via is provided through the substrate between the first surface and the second surface, and the via is electrically conductive. In an embodiment, a layer in contact with the sidewall of the substrate surrounds a perimeter of the substrate.

公开(公告)号：US20220199515A1

公开(公告)日：2022-06-23

申请号：US17690964

申请日：2022-03-09

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Jung Kyu HAN ,  Ali LEHAF ,  Steve CHO ,  Thomas HEATON ,  Hiroki TANAKA ,  Kristof DARMAWIKARTA ,  Robert Alan MAY ,  Sri Ranga Sai BOYAPATI

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00

Abstract: A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration.

公开(公告)号：US20210066162A1

公开(公告)日：2021-03-04

申请号：US16557896

申请日：2019-08-30

Applicant: Intel Corporation

Inventor： Sergio A. CHAN ARGUEDAS ,  Nicholas S. HAEHN ,  Edvin CETEGEN ,  Nicholas NEAL ,  Jacob VEHONSKY ,  Steve S. CHO ,  Rahul JAIN ,  Antariksh Rao Pratap SINGH ,  Tarek A. IBRAHIM ,  Thomas HEATON ,  Vipul MEHTA

IPC: H01L23/42 ,  H01L23/00

Abstract: A device is disclosed. The device includes a substrate, a die on the substrate, a thermal interface material (TIM) on the die, and solder bumps on a periphery of a top surface of the substrate. An integrated heat spreader (IHS) is formed on the solder bumps. The IHS covers the TIM.

公开(公告)号：US20210020532A1

公开(公告)日：2021-01-21

申请号：US16511376

申请日：2019-07-15

Applicant: Intel Corporation

Inventor： Jacob VEHONSKY ,  Nicholas S. HAEHN ,  Thomas HEATON ,  Steve S. CHO ,  Rahul JAIN ,  Tarek IBRAHIM ,  Antariksh Rao Pratap SINGH ,  Edvin CETEGEN ,  Nicholas NEAL ,  Sergio CHAN ARGUEDAS

IPC: H01L23/16 ,  H01L23/498 ,  H01L23/00 ,  H01L23/367

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment an electronic package comprises a package substrate, and a first level interconnect (FLI) bump region on the package substrate. In an embodiment, the FLI bump region comprises a plurality of pads, and a plurality of bumps, where each bump is over a different one of the plurality of pads. In an embodiment, the electronic package further comprises a guard feature adjacent to the FLI bump region. In an embodiment, the guard feature comprises, a guard pad, and a guard bump over the guard pad, wherein the guard feature is electrically isolated from circuitry of the electronic package.

公开(公告)号：US20210020531A1

公开(公告)日：2021-01-21

申请号：US16511360

申请日：2019-07-15

Applicant: Intel Corporation

Inventor： Edvin CETEGEN ,  Jacob VEHONSKY ,  Nicholas S. HAEHN ,  Thomas HEATON ,  Steve S. CHO ,  Rahul JAIN ,  Tarek IBRAHIM ,  Antariksh Rao Pratap SINGH ,  Nicholas NEAL ,  Sergio CHAN ARGUEDAS ,  Vipul MEHTA

IPC: H01L23/16 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: Embodiments disclosed herein include electronic packages with underfill flow control features. In an embodiment, an electronic package comprises a package substrate and a plurality of interconnects on the package substrate. In an embodiment, a die is coupled to the package substrate by the plurality of interconnects and a flow control feature is adjacent on the package substrate. In an embodiment, the flow control feature is electrically isolated from circuitry of the electronic package. In an embodiment, the electronic package further comprises an underfill surrounding the plurality of interconnects and in contact with the flow control feature.

公开(公告)号：US20240243088A1

公开(公告)日：2024-07-18

申请号：US18622486

申请日：2024-03-29

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Jung Kyu HAN ,  Thomas HEATON ,  Ali LEHAF ,  Rahul MANEPALLI ,  Srinivas PIETAMBARAM ,  Jacob VEHONSKY

IPC: H01L23/00 ,  C25D3/38 ,  C25D5/02 ,  C25D7/12

CPC classification number: H01L24/14 ,  C25D3/38 ,  C25D5/022 ,  C25D7/12 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/1111 ,  H01L2224/11462 ,  H01L2224/13147 ,  H01L2224/1403

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to manufacturing a package having a substrate with a first side and a second side opposite the first side, where a copper layer is coupled with a first region of the first side of the substrate and includes a plurality of bumps coupled with the first region of the first side of the substrate where one or more second regions on the first side of the substrate not coupled with a copper layer, and where a layout of the one or more second regions on the first side of the substrate is to vary a growth, respectively, of each of the plurality of bumps during a plating process by modifying a local copper density of each of the plurality of bumps.