公开(公告)号：US20230268291A1

公开(公告)日：2023-08-24

申请号：US17679189

申请日：2022-02-24

Applicant: Intel Corporation

Inventor： Mohan Prashanth Javare Gowda ,  Stephan Stoeckl ,  Sonja Koller ,  Wolfgang Molzer ,  Thomas Wagner ,  Pouya Talebbeydokhti

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/552

CPC classification number: H01L23/562 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/552

Abstract: Embodiments of a microelectronic assembly include a package substrate comprising: a first layer comprising a first plurality of mutually parallel channels of a first material; a second layer comprising columns of the first material; and a third layer comprising a second plurality of mutually parallel channels of the first material, the second plurality of mutually parallel channels being orthogonal to the first plurality of mutually parallel channels. The second layer is between the first layer and the third layer, at least some columns extend between and contact the first plurality of mutually parallel channels and the second plurality of mutually parallel channels, and at least a portion of the first layer, the second layer and the third layer comprises a second material different from the first material.

公开(公告)号：US20230268286A1

公开(公告)日：2023-08-24

申请号：US17679185

申请日：2022-02-24

Applicant: Intel Corporation

Inventor： Mohan Prashanth Javare Gowda ,  Stephan Stoeckl ,  Thomas Wagner ,  Sonja Koller ,  Wolfgang Molzer ,  Pouya Talebbeydokhti

IPC: H01L23/552 ,  H01L23/498

CPC classification number: H01L23/552 ,  H01L23/49822 ,  H01L23/49827

Abstract: Embodiments of a microelectronic assembly comprise a package substrate, including: a first layer comprising a first plurality of mutually parallel channels of a first material; a second layer comprising columns of the first material; and a third layer comprising a second plurality of mutually parallel channels of the first material. The second layer is between the first layer and the third layer, at least some columns extend between and contact the first plurality of mutually parallel channels and the second plurality of mutually parallel channels, and at least a portion of the first layer, the second layer, and the third layer comprises a second material different from the first material.

公开(公告)号：US12057411B2

公开(公告)日：2024-08-06

申请号：US16721095

申请日：2019-12-19

Applicant: Intel Corporation

Inventor： Stephan Stoeckl ,  Wolfgang Molzer ,  Georg Seidemann ,  Bernd Waidhas

IPC: H01L23/58 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L49/02 ,  H01L23/00

CPC classification number: H01L23/585 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3128 ,  H01L28/40 ,  H01L24/13 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/13024

Abstract: Embodiments disclosed herein include semiconductor packages. In a particular embodiment, the semiconductor package is a wafer level chip scale package (WLCSP). In an embodiment, the WLCSP comprises a die. In an embodiment, the die comprises an active surface and a backside surface. The die has a first coefficient of thermal expansion (CTE). In an embodiment, the WLCSP further comprises a channel into the die. In an embodiment, the channel is filled with a stress relief material, where the stress relief material has a second CTE that is greater than the first CTE.

公开(公告)号：US20230307313A1

公开(公告)日：2023-09-28

申请号：US17703400

申请日：2022-03-24

Applicant: Intel Corporation

Inventor： Carlton Hanna ,  Wolfgang Molzer ,  Stefan Reif ,  Georg Seidemann ,  Stephan Stoeckl ,  Pouya Talebbeydokhti

IPC: H01L23/373 ,  H01L23/367

CPC classification number: H01L23/3732 ,  H01L23/367

Abstract: A semiconductor package comprises a package substrate comprised of at least a first layer of dielectric material including a portion of diamond dust material. The diamond dust material is comprised of diamond dust particles. The semiconductor package includes at least one electrical connection coupled through layers of the package substrate.

公开(公告)号：US20190006318A1

公开(公告)日：2019-01-03

申请号：US15637935

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Georg Seidemann ,  Andreas Augustin ,  Laurent Millou ,  Andreas Wolter ,  Reinhard Mahnkopf ,  Stephan Stoeckl ,  Thomas Wagner

IPC: H01L25/065 ,  H01L21/48 ,  H01L23/48

CPC classification number: H01L25/0657 ,  G06F15/76 ,  H01L21/486 ,  H01L23/481 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/1011 ,  H01L2225/1017 ,  H01L2225/1058

Abstract: A semiconductive device stack, includes a baseband processor die with an active surface and a backside surface, and a recess in the backside surface. A recess-seated device is disposed in the recess, and a through-silicon via in the baseband processor die couples the baseband processor die at the active surface to the recess-seated die at the recess. A processor die is disposed on the baseband processor die backside surface, and a memory die is disposed on the processor die. The several dice are coupled by through-silicon via groups.

公开(公告)号：US09368461B2

公开(公告)日：2016-06-14

申请号：US14280110

申请日：2014-05-16

Applicant: INTEL CORPORATION

Inventor： Sven Albers ,  Georg Seidemann ,  Sonja Koller ,  Stephan Stoeckl ,  Shubhada H. Sahasrabudhe ,  Sandeep B. Sane

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/05 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/141 ,  H01L2224/16238 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/111 ,  H05K3/3436 ,  H05K2201/0373

Abstract: Disclosed herein are contact pads for use with integrated circuit (IC) packages. In some embodiments, a contact pad disclosed herein may be disposed on a substrate of an IC package, and may include a metal projection portion and a metal recess portion. Each of the metal projection portion and the metal recess portion may have a solder contact surface. The solder contact surface of the metal recess portion may be spaced away from the solder contact surface of the metal projection portion. Related devices and techniques are also disclosed herein, and other embodiments may be claimed.

Abstract translation: 这里公开了与集成电路（IC）封装一起使用的接触焊盘。 在一些实施例中，本文公开的接触垫可以设置在IC封装的基板上，并且可以包括金属突出部分和金属凹部。 金属突出部和金属凹部中的每一个可以具有焊料接触表面。 金属凹部的焊接接触表面可以与金属突出部的焊接接触表面间隔开。 本文还公开了相关的设备和技术，并且可以要求保护其他实施例。

公开(公告)号：US11374323B2

公开(公告)日：2022-06-28

申请号：US16473566

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Andreas Augustin ,  Sonja Koller ,  Bernd Waidhas ,  Georg Seidemann ,  Andreas Wolter ,  Stephan Stoeckl ,  Thomas Wagner ,  Josef Hagn

IPC: H01Q9/04 ,  H01L23/00 ,  H01Q1/22 ,  H01Q21/06

Abstract: A patch antenna array is fabricated with a package-on-package setup that contains a transceiver. The patch antenna array has a footprint that intersects the transceiver footprint. The package-on-package setup includes through-mold vias that couple to a redistribution layer disposed between the patch antennas and the package-on-package setup.

公开(公告)号：US10403602B2

公开(公告)日：2019-09-03

申请号：US15637935

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Georg Seidemann ,  Andreas Augustin ,  Laurent Millou ,  Andreas Wolter ,  Reinhard Mahnkopf ,  Stephan Stoeckl ,  Thomas Wagner

IPC: H01L21/48 ,  H01L25/065 ,  H01L23/48 ,  G06F15/76 ,  H01L25/00

Abstract: A semiconductive device stack, includes a baseband processor die with an active surface and a backside surface, and a recess in the backside surface. A recess-seated device is disposed in the recess, and a through-silicon via in the baseband processor die couples the baseband processor die at the active surface to the recess-seated die at the recess. A processor die is disposed on the baseband processor die backside surface, and a memory die is disposed on the processor die. The several dice are coupled by through-silicon via groups.

公开(公告)号：US20230317705A1

公开(公告)日：2023-10-05

申请号：US17707366

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： Carlton Hanna ,  Bernd Waidhas ,  Georg Seidemann ,  Stephan Stoeckl ,  Pouya Talebbeydokhti ,  Stefan Reif ,  Eduardo De Mesa ,  Abdallah Bacha ,  Mohan Prashanth Javare Gowda ,  Lizabeth Keser

IPC: H01L25/18 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H01L25/00 ,  H05K1/18

CPC classification number: H01L25/18 ,  H01L23/5384 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H05K1/181 ,  H01L2225/06572 ,  H01L2225/06517 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1094 ,  H05K2201/09072 ,  H05K2201/10378 ,  H05K2201/10734

Abstract: An electronic system has a printed circuit board and a substrate. The substrate has two sides, a top and bottom. At least one memory unit is connected to the bottom side of the substrate and at least one processor is connected to the top side of the substrate. The memory is connected to the processor with interconnects that pass through the substrate.

公开(公告)号：US20230298953A1

公开(公告)日：2023-09-21

申请号：US17699139

申请日：2022-03-20

Applicant: Intel Corporation

Inventor： Pouya Talebbeydokhti ,  Mohan Prashanth Javare Gowda ,  Sonja Koller ,  Stephan Stoeckl ,  Thomas Wagner ,  Wolfgang Molzer

IPC: H01L23/053 ,  H01L23/00 ,  H01L25/10 ,  H01L23/06 ,  H01L23/10

CPC classification number: H01L23/053 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/105 ,  H01L23/06 ,  H01L23/10 ,  H01L2224/73204 ,  H01L2224/32225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16237 ,  H01L2924/35121 ,  H01L2924/37001 ,  H01L2924/3511 ,  H01L2924/1611 ,  H01L2924/16251 ,  H01L2924/1631 ,  H01L2924/16315 ,  H01L2924/1632

Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a substrate; a lid surrounding an individual die, wherein the lid includes a planar portion and two or more sides extending from the planar portion, and wherein the individual die is electrically coupled to the substrate by interconnects; and a material surrounding the interconnects and coupling the two or more sides of the lid to the substrate.