公开(公告)号：US20220216131A1

公开(公告)日：2022-07-07

申请号：US17560196

申请日：2021-12-22

Applicant: XINTEC INC.

Inventor： Po-Han LEE ,  Wei-Ming CHIEN

IPC: H01L23/48 ,  H01L29/20 ,  H01L23/498

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a first surface and a second surface opposite thereto. A gallium nitride (GaN)-based device layer is formed on the first surface of the semiconductor substrate and has source, drain, and gate contact regions. First, second, and third through-substrate vias (TSVs) pass through the semiconductor substrate and are respectively electrically connected to the source, drain, and gate contact regions. An insulating liner layer is formed on the second surface of the semiconductor substrate and extends into the semiconductor substrate to separate the second and third TSVs from the semiconductor substrate. A semiconductor package assembly including the semiconductor device structure is also provided.

公开(公告)号：US20210082841A1

公开(公告)日：2021-03-18

申请号：US17023199

申请日：2020-09-16

Applicant: XINTEC INC.

Inventor： Po-Han LEE ,  Chia-Ming CHENG ,  Jiun-Yen LAI ,  Ming-Chung CHUNG ,  Wei-Luen SUEN

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/552 ,  H01L21/3213

Abstract: A chip package includes a semiconductor substrate, a supporting element, an antenna layer, and a redistribution layer. The semiconductor substrate has an inclined sidewall and a conductive pad that protrudes from the inclined sidewall. The supporting element is located on the semiconductor substrate, and has a top surface facing away from the semiconductor substrate, and has an inclined sidewall adjoining the top surface. The antenna layer is located on the top surface of the supporting element. The redistribution layer is located on the inclined sidewall of the supporting element, and is in contact with a sidewall of the conductive pad and an end of the antenna.

公开(公告)号：US20160111555A1

公开(公告)日：2016-04-21

申请号：US14971395

申请日：2015-12-16

Applicant: XINTEC INC.

Inventor： Tsang-Yu LIU ,  Shu-Ming CHANG ,  Po-Han LEE

IPC: H01L31/0203 ,  H01L31/02 ,  H01L31/18

CPC classification number: H01L31/0203 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/12 ,  H01L24/13 ,  H01L31/02005 ,  H01L31/18 ,  H01L2224/131 ,  H01L2224/73253 ,  Y02P70/521 ,  H01L2924/014

Abstract: A method of manufacturing chip package includes providing a semiconductor wafer having a plurality of semiconductor chips. An outer spacer and a plurality of inner spacers are formed on the semiconductor wafer. A protection lid is formed and disposed on the outer spacer and the inner spacers. A plurality of cavities is formed on each of the semiconductor chips from a lower surface thereof to expose the conductive pad disposed on the upper surface of the semiconductor chip. A plurality of conductive portions is formed and fills each of the cavities and electrically connected to each of the conductive pads. A plurality of solder balls is disposed on the lower surface and electrically connected to each of the conductive portions. The semiconductor chips are separated by cutting along a plurality of cutting lines between each of the semiconductor chips.

Abstract translation: 制造芯片封装的方法包括提供具有多个半导体芯片的半导体晶片。 在半导体晶片上形成有外隔离物和多个内隔离物。 保护盖形成并设置在外隔离件和内间隔件上。 从其下表面在每个半导体芯片上形成多个空腔，以露出设置在半导体芯片的上表面上的导电焊盘。 形成多个导电部分，并填充每个空腔并电连接到每个导电焊盘。 多个焊球设置在下表面并电连接到每个导电部分。 半导体芯片通过沿着每个半导体芯片之间的多个切割线进行切割来分离。

公开(公告)号：US20150295097A1

公开(公告)日：2015-10-15

申请号：US14682888

申请日：2015-04-09

Applicant: XINTEC INC.

Inventor： Tsang-Yu LIU ,  Shu-Ming CHANG ,  Po-Han LEE

IPC: H01L31/0203 ,  H01L31/02 ,  H01L31/18

CPC classification number: H01L31/0203 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/12 ,  H01L24/13 ,  H01L31/02005 ,  H01L31/18 ,  H01L2224/131 ,  H01L2224/73253 ,  Y02P70/521 ,  H01L2924/014

Abstract: A chip package includes semiconductor chips, inner spacers, cavities, conductive portions and solder balls. The semiconductor chip has at least an electronic component and at least an electrically conductive pad disposed on an upper surface thereof. The conductive pad is arranged abreast to one side of the electronic component and electrically connected thereto. The cavities open to a lower surface of the semiconductor chip and extend toward the upper surface to expose the conductive pad on the upper surface. The conductive portions fill the cavities from the lower surface and electrically connected the to conductive pad. The solder balls are disposed on the lower surface and electrically connected to the conductive portions. A gap is created between an outer wall of the inner spacers and an edge of the semiconductor chip.

Abstract translation: 芯片封装包括半导体芯片，内部间隔件，空腔，导电部分和焊球。 半导体芯片至少具有电子部件，并且至少设置在其上表面上的导电焊盘。 导电焊盘与电子部件的一侧并排设置并与之电连接。 空腔通向半导体芯片的下表面并朝向上表面延伸以暴露上表面上的导电焊盘。 导电部分从下表面填充空腔并电连接到导电垫。 焊球设置在下表面上并电连接到导电部分。 在内隔板的外壁和半导体芯片的边缘之间产生间隙。

公开(公告)号：US20150123285A1

公开(公告)日：2015-05-07

申请号：US14592840

申请日：2015-01-08

Applicant: XINTEC INC.

Inventor： Chia-Sheng LIN ,  Po-Han LEE

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/481 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76898 ,  H01L21/78 ,  H01L21/784 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/3192 ,  H01L23/5389 ,  H01L23/564 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/73 ,  H01L24/83 ,  H01L24/94 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14636 ,  H01L27/14687 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/29011 ,  H01L2224/29082 ,  H01L2224/2919 ,  H01L2224/73253 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00014

Abstract: A chip device package and a fabrication method thereof are provided. The chip device package includes a semiconductor substrate having a first surface and an opposing second surface. A recessed portion is disposed adjacent to a sidewall of the semiconductor substrate, extending from the first surface of the semiconductor substrate to at least the second surface of the semiconductor substrate. A protection layer is disposed over the first surface of the semiconductor substrate and in the recessed portion. A through hole is disposed on the first surface of the semiconductor substrate. A buffer material that is different from the material of the protection layer is disposed in the through hole and covered by the protection layer.

Abstract translation: 提供了一种芯片器件封装及其制造方法。 芯片器件封装包括具有第一表面和相对的第二表面的半导体衬底。 凹部与半导体衬底的侧壁相邻地设置，从半导体衬底的第一表面延伸到半导体衬底的至少第二表面。 保护层设置在半导体衬底的第一表面和凹部中。 在半导体衬底的第一表面上设置通孔。 与保护层的材料不同的缓冲材料设置在通孔中并被保护层覆盖。

公开(公告)号：US20230361144A1

公开(公告)日：2023-11-09

申请号：US18304325

申请日：2023-04-20

Applicant: Xintec Inc.

Inventor： Wei-Ming CHIEN ,  Po-Han LEE ,  Tsang Yu LIU ,  Joey LAI

IPC: H01L27/146

CPC classification number: H01L27/14632 ,  H01L27/14621 ,  H01L27/14623

Abstract: A chip package includes a light transmissive sheet, a chip, a bonding layer, and an insulating layer. The light transmissive sheet has a protruding portion. A first surface of the chip faces toward the light transmissive sheet and has a sensing area. The bonding layer is located between the chip and the light transmissive sheet. The sum of a thickness of the chip and a thickness of the bonding layer is greater than or equal to a thickness of the light transmissive sheet. A protruding portion of the light transmissive sheet protrudes from a sidewall of the chip and a sidewall of the bonding layer. The insulating layer extends from a second surface of the chip to the protruding portion of the light transmissive sheet along the sidewall of the chip and the sidewall of the bonding layer.

公开(公告)号：US20170179330A1

公开(公告)日：2017-06-22

申请号：US15451202

申请日：2017-03-06

Applicant: XINTEC INC.

Inventor： Wei-Luen SUEN ,  Wei-Ming CHIEN ,  Po-Han LEE ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC: H01L31/18 ,  H01L31/0203 ,  H01L31/0236 ,  H01L31/02

CPC classification number: H01L31/02327 ,  H01L21/561 ,  H01L23/3114 ,  H01L31/02002 ,  H01L31/0203 ,  H01L31/02363 ,  H01L31/1804 ,  H01L2224/11

Abstract: A semiconductor structure includes a silicon substrate, a protection layer, an electrical pad, an isolation layer, a redistribution layer, a conductive layer, a passivation layer, and a conductive structure. The silicon substrate has a concave region, a step structure, a tooth structure, a first surface, and a second surface opposite to the first surface. The step structure and the tooth structure surround the concave region. The step structure has a first oblique surface, a third surface, and a second oblique surface facing the concave region and connected in sequence. The protection layer is located on the first surface of the silicon substrate. The electrical pad is located in the protection layer and exposed through the concave region. The isolation layer is located on the first and second oblique surfaces, the second and third surfaces of the step structure, and the tooth structure.

公开(公告)号：US20170148752A1

公开(公告)日：2017-05-25

申请号：US15351309

申请日：2016-11-14

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Chia-Sheng LIN ,  Po-Han LEE ,  Wei-Luen SUEN

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/02 ,  H01L24/03 ,  H01L24/13 ,  H01L2224/0214 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/0231 ,  H01L2224/0235 ,  H01L2224/0239 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05016 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05567 ,  H01L2224/05582 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/13022 ,  H01L2224/13026 ,  H01L2224/131 ,  H01L2924/01013 ,  H01L2924/06 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A chip package includes a substrate, an isolation layer, a redistribution layer, a passivation layer, a first conductive layer, a second conductive layer, and a conductive structure. The isolation layer is located on the substrate. The redistribution layer is located on the isolation layer. The passivation layer is located on the isolation layer and the redistribution layer. The passivation layer has an opening, a wall surface that surrounds the opening, and a surface that faces away from the isolation layer. A portion of the redistribution layer is exposed through the opening. The first conductive layer is located on the redistribution layer that is in the opening, and extends to the wall surface and the surface of the passivation layer. The second conductive layer covers the first conductive layer. The conductive structure is located on the second conductive layer and protrudes from the passivation layer.

公开(公告)号：US20170117242A1

公开(公告)日：2017-04-27

申请号：US15297490

申请日：2016-10-19

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Tsang-Yu LIU ,  Po-Han LEE ,  Chi-Chang LIAO

IPC: H01L23/00

CPC classification number: H01L24/16 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/06181 ,  H01L2224/08265 ,  H01L2224/1403 ,  H01L2224/14155 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/171 ,  H01L2224/29011 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/146

Abstract: A chip package is provided. The chip package includes a substrate. The substrate includes a sensing region or device region. The chip package also includes a first conducting structure disposed on the substrate. The first conducting structure is electrically connected to the sensing region or device region. The chip package further includes a passive element vertically stacked on the substrate. The passive element and the first conducting structure are positioned side by side.

公开(公告)号：US20170110495A1

公开(公告)日：2017-04-20

申请号：US15277184

申请日：2016-09-27

Applicant: XINTEC INC.

Inventor： Jyun-Liang WU ,  Chia-Sheng LIN ,  Po-Han LEE ,  Yen-Shih HO

IPC: H01L27/146 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L27/14618 ,  H01L21/563 ,  H01L24/03 ,  H01L24/08 ,  H01L2224/0231 ,  H01L2224/0237

Abstract: A chip package includes a chip, a dam element, and a height-increasing element. The chip has an image sensing area, a first surface, and a second surface opposite to the first surface. The image sensing area is located on the first surface of the chip. The dam element is located on the first surface of the chip and surrounds the image sensing area. The height-increasing element is located on the dam element, such that the dam element is between the height-increasing element and the chip.