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    Barrier material and process for Cu interconnect
    92.
    发明授权
    Barrier material and process for Cu interconnect 有权
    铜互连的阻挡材料和工艺

    公开(公告)号：US08178437B2

    公开(公告)日：2012-05-15

    申请号：US12181770

    申请日：2008-07-29

    Applicant: Chung-Liang Chang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

    Inventor： Chung-Liang Chang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

    IPC: H01L21/4763

    CPC classification number: H01L21/76846 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76864 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor diffusion barrier layer and its method of manufacture is described. The barrier layer includes of at least one layer of TaN, TiN, WN, TbN, VN, ZrN, CrN, WC, WN, WCN, NbN, AlN, and combinations thereof. The barrier layer may further include a metal rich surface. Embodiments preferably include a glue layer about 10 to 500 Angstroms thick, the glue layer consisting of Ru, Ta, Ti, W, Co, Ni, Al, Nb, AlCu, and a metal-rich nitride, and combinations thereof. The ratio of the glue layer thickness to the barrier layer thickness is preferably about 1 to 50. Other alternative preferred embodiments further include a conductor annealing step. The various layers may be deposited using PVD, CVD, PECVD, PEALD and/or ALD methods including nitridation and silicidation methods.

    Abstract translation: 描述了半导体扩散阻挡层及其制造方法。 阻挡层包括至少一层TaN，TiN，WN，TbN，VN，ZrN，CrN，WC，WN，WCN，NbN，AlN及其组合。 阻挡层还可以包括富金属表面。 实施例优选包括约10至500埃厚的胶层，由Ru，Ta，Ti，W，Co，Ni，Al，Nb，AlCu和富含金属的氮化物组成的胶层及其组合。 胶层厚度与阻挡层厚度的比率优选为约1〜50。其他优选实施方案还包括导体退火步骤。 可以使用PVD，CVD，PECVD，PEALD和/或ALD方法沉积各种层，包括氮化和硅化方法。

    LOW RESISTANCE HIGH RELIABILITY CONTACT VIA AND METAL LINE STRUCTURE FOR SEMICONDUCTOR DEVICE
    93.
    发明申请
    LOW RESISTANCE HIGH RELIABILITY CONTACT VIA AND METAL LINE STRUCTURE FOR SEMICONDUCTOR DEVICE 有权
    低电阻高可靠性接触半导体器件的金属线结构

    公开(公告)号：US20110024908A1

    公开(公告)日：2011-02-03

    申请号：US12845852

    申请日：2010-07-29

    Applicant: Hsiang-Huan Lee ,  Ming Han Lee ,  Ming-Shih Yeh ,  Chen-Hua Yu ,  Shau-Lin Shue

    Inventor： Hsiang-Huan Lee ,  Ming Han Lee ,  Ming-Shih Yeh ,  Chen-Hua Yu ,  Shau-Lin Shue

    IPC: H01L23/52 ,  H01L21/4763

    CPC classification number: H01L23/53238 ,  H01L21/28562 ,  H01L21/76846 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76883 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The structures and methods described above provide mechanisms to improve interconnect reliability and resistivity. The interconnect reliability and resistivity are improved by using a composite barrier layer, which provides good step coverage, good copper diffusion barrier, and good adhesion with adjacent layers. The composite barrier layer includes an ALD barrier layer to provide good step coverage. The composite barrier layer also includes a barrier-adhesion-enhancing film, which contains at least an element or compound that contains Mn, Cr, V, Ti, or Nb to improve adhesion. The composite barrier layer may also include a Ta or Ti layer between the ALD barrier layer and the barrier-adhesion-enhancing layer.

    Abstract translation: 上述结构和方法提供了提高互连可靠性和电阻率的机制。 通过使用复合阻挡层来提高互连的可靠性和电阻率，该复合阻挡层提供良好的台阶覆盖率，良好的铜扩散阻挡层和与相邻层的良好粘附性。 复合阻挡层包括ALD阻挡层以提供良好的阶梯覆盖。 复合阻挡层还包括至少包含含有Mn，Cr，V，Ti或Nb的元素或化合物以提高粘合性的阻隔增粘膜。 复合阻挡层还可以包括在ALD阻挡层和阻挡增粘层之间的Ta或Ti层。

    METHOD FOR MAKING A THERMALLY-STABLE SILICIDE
    96.
    发明申请
    METHOD FOR MAKING A THERMALLY-STABLE SILICIDE 审中-公开
    制备耐热硅酮的方法

    公开(公告)号：US20100151639A1

    公开(公告)日：2010-06-17

    申请号：US12712518

    申请日：2010-02-25

    Applicant: Shau-Lin Shue ,  Chen-Hua Yu ,  Cheng-Tung Lin ,  Chii-Ming Wu ,  Shih-Wei Chou ,  Gin Jei Wang ,  CP Lo ,  Chih-Wei Chang

    Inventor： Shau-Lin Shue ,  Chen-Hua Yu ,  Cheng-Tung Lin ,  Chii-Ming Wu ,  Shih-Wei Chou ,  Gin Jei Wang ,  CP Lo ,  Chih-Wei Chang

    IPC: H01L21/336 ,  H01L21/28

    CPC classification number: H01L29/665 ,  H01L21/76243 ,  H01L29/785

    Abstract: Provided is a method of fabrication a semiconductor device that includes providing a semiconductor substrate, forming a gate structure over the substrate, the gate structure including a gate dielectric and a gate electrode disposed over the gate dielectric, forming source/drain regions in the semiconductor substrate at either side of the gate structure, forming a metal layer over the semiconductor substrate and the gate structure, the metal layer including a refractory metal layer or a refractory metal compound layer; forming an alloy layer over the metal layer; and performing an annealing thereby forming metal alloy silicides over the gate structure and the source/drain regions, respectively.

    Abstract translation: 提供一种制造半导体器件的方法，其包括提供半导体衬底，在衬底上形成栅极结构，栅极结构包括栅极电介质和设置在栅极电介质上的栅电极，在半导体衬底中形成源极/漏极区域 在栅极结构的任一侧，在半导体衬底和栅极结构之上形成金属层，金属层包括难熔金属层或难熔金属化合物层; 在所述金属层上形成合金层; 并进行退火，从而分别在栅极结构和源极/漏极区域上形成金属合金硅化物。

    METHOD AND APPARATUS FOR ELECTROCHEMICAL PLATING SEMICONDUCTOR WAFERS
    97.
    发明申请
    METHOD AND APPARATUS FOR ELECTROCHEMICAL PLATING SEMICONDUCTOR WAFERS 有权
    电化学半导体波导的方法和装置

    公开(公告)号：US20100140099A1

    公开(公告)日：2010-06-10

    申请号：US12705903

    申请日：2010-02-15

    Applicant: Chung-Liang Chang ,  Shau-Lin Shue

    Inventor： Chung-Liang Chang ,  Shau-Lin Shue

    IPC: C25D5/00 ,  C25D5/34 ,  C25D3/02 ,  C25D17/00

    CPC classification number: H01L21/2885 ,  C25D5/18 ,  C25D7/123 ,  C25D17/001 ,  C25D17/007 ,  H01L21/76877

    Abstract: A method of electroplating conductive material on semiconductor wafers controls undesirable surface defects by reducing the electroplating current as the wafer is being initially immersed in a plating bath. Further defect reduction and improved bottom up plating of vias is achieved by applying a static charge on the wafer before it is immersed in the bath, in order to enhance bath accelerators used to control the plating rate. The static charge is applied to the wafer using a supplemental electrode disposed outside the plating bath.

    Abstract translation: 在半导体晶片上电镀导电材料的方法通过在晶片最初浸入电镀槽中时减少电镀电流来控制不期望的表面缺陷。 通过在晶片浸入槽中之前对晶片施加静电电荷，以便增强用于控制电镀速率的浴加速器，可实现进一步的缺陷减少和改进的底部电镀通孔。 使用布置在电镀液外部的辅助电极将静电荷施加到晶片。

    SEMICONDUCTOR INTERCONNECTION STRUCTURE AND METHOD FOR MAKING THE SAME
    99.
    发明申请
    SEMICONDUCTOR INTERCONNECTION STRUCTURE AND METHOD FOR MAKING THE SAME 审中-公开
    半导体互连结构及其制造方法

    公开(公告)号：US20090117731A1

    公开(公告)日：2009-05-07

    申请号：US11934005

    申请日：2007-11-01

    Applicant: Chen-Hua Yu ,  Shau-Lin Shue ,  Chien-Hsueh Shih ,  Ming-Shih Yeh ,  Ming-Han Lee

    Inventor： Chen-Hua Yu ,  Shau-Lin Shue ,  Chien-Hsueh Shih ,  Ming-Shih Yeh ,  Ming-Han Lee

    IPC: H01L21/4763

    CPC classification number: H01L21/76844 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76877 ,  H01L2221/1089

    Abstract: A semiconductor interconnection structure is manufactured as follows. First, a substrate with a first dielectric layer and a second dielectric layer is formed. Subsequently, an opening is formed in the second dielectric layer. A thin metal layer and a seed layer are formed in sequence on the surface of the second dielectric layer in the opening, wherein the metal layer comprises at least one metal species having phase segregation property of a second conductor. The wafer of the substrate is subjected to a thermal treatment, by which most of the metal species in the metal layer at a bottom of the opening is diffused to a top surface of the second conductor to form a metal-based oxide layer. Afterwards, the wafer is subjected to planarization, so as to remove the second conductor outside the opening.

    Abstract translation: 如下制造半导体互连结构。 首先，形成具有第一介电层和第二介质层的基板。 随后，在第二电介质层中形成开口。 在开口中的第二电介质层的表面上依次形成薄金属层和种子层，其中金属层包含至少一种具有第二导体的相分离特性的金属物质。 对基板的晶片进行热处理，通过该热处理，开口底部的金属层中的大部分金属物质扩散到第二导体的顶表面，形成金属基氧化物层。 然后，对晶片进行平面化处理，以便将开口外的第二导体移除。

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