公开(公告)号：US6153261A

公开(公告)日：2000-11-28

申请号：US322709

申请日：1999-05-28

申请人： Li-Qun Xia ,  Ellie Yieh

发明人： Li-Qun Xia ,  Ellie Yieh

IPC分类号： C23C16/34 ,  C23C16/40 ,  C23C16/52 ,  H01L21/312 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  C23C16/30

CPC分类号： H01L21/0214 ,  C23C16/345 ,  C23C16/402 ,  C23C16/52 ,  H01L21/0217 ,  H01L21/02222 ,  H01L21/02271 ,  H01L21/3145 ,  H01L21/31612 ,  H01L21/3185 ,  H01L21/3122

摘要： A method and an apparatus for increasing a deposition rate of dielectric films deposited on a substrate for a given temperature while providing the same with good step coverage and gap-fill properties. This is achieved by employing bistertiarybutylaminesilane as a silicon source to react with an oxidizing agent to form a dielectric film on a substrate that includes silicon.

摘要翻译： 一种用于提高沉积在基底上的介电膜在给定温度下的沉积速率的方法和装置，同时提供良好的阶梯覆盖和间隙填充性能。 这通过使用二乙基丁基胺硅作为硅源与氧化剂反应以在包括硅的衬底上形成电介质膜来实现。

公开(公告)号：US5935340A

公开(公告)日：1999-08-10

申请号：US747892

申请日：1996-11-13

申请人： Li-Qun Xia ,  Visweswaren Sivaramakrishnan ,  Srinivas Nemani ,  Ellie Yieh ,  Gary Fong

发明人： Li-Qun Xia ,  Visweswaren Sivaramakrishnan ,  Srinivas Nemani ,  Ellie Yieh ,  Gary Fong

IPC分类号： B08B7/00 ,  C23C16/44 ,  H01L21/00 ,  B08B6/00

CPC分类号： H01L21/67017 ,  B08B7/0035 ,  C23C16/4405

摘要： The present invention provides systems, methods and apparatus for high temperature (at least about 500-800.degree. C.) processing of semiconductor wafers. The systems, methods and apparatus of the present invention allow multiple process steps to be performed in situ in the same chamber to reduce total processing time and to ensure high quality processing for high aspect ratio devices. Performing multiple process steps in the same chamber also increases the control of the process parameters and reduces device damage. In particular, the present invention can provide high temperature deposition, heating and efficient cleaning for forming dielectric films having thickness uniformity, good gap fill capability, high density, low moisture, and other desired characteristics.

摘要翻译： 本发明提供用于半导体晶片的高温（至少约500-800℃）处理的系统，方法和装置。 本发明的系统，方法和装置允许多个工艺步骤在相同的腔室中原位进行，以减少总处理时间，并确保对高纵横比器件的高质量处理。 在同一个室内执行多个工艺步骤也可以增加工艺参数的控制并减少设备损坏。 特别地，本发明可以提供用于形成具有厚度均匀性，良好间隙填充能力，高密度，低湿度和其它所需特性的介电膜的高温沉积，加热和有效清洁。

公开(公告)号：US09748125B2

公开(公告)日：2017-08-29

申请号：US13755891

申请日：2013-01-31

申请人： Banqiu Wu ,  Nag B. Patibandla ,  Toshiaki Fujita ,  Ralf Hofmann ,  Pravin K. Narwankar ,  Jeonghoon Oh ,  Srinivas Satya ,  Li-Qun Xia

发明人： Banqiu Wu ,  Nag B. Patibandla ,  Toshiaki Fujita ,  Ralf Hofmann ,  Pravin K. Narwankar ,  Jeonghoon Oh ,  Srinivas Satya ,  Li-Qun Xia

IPC分类号： C23C16/00 ,  H01L21/00 ,  H01L21/673 ,  H01L21/677 ,  C23C16/455 ,  C23C16/458 ,  C23C16/54

CPC分类号： H01L21/673 ,  C23C16/45546 ,  C23C16/4558 ,  C23C16/4584 ,  C23C16/54 ,  H01L21/67346 ,  H01L21/677

摘要： A processing chamber having a plurality of movable substrate carriers stacked therein for continuously processing a plurality of substrates is provided. The movable substrate carrier is capable of being transported from outside of the processing chamber, e.g., being transferred from a load luck chamber, into the processing chamber and out of the processing chamber, e.g., being transferred into another load luck chamber. Process gases delivered into the processing chamber are spatially separated into a plurality of processing slots, and/or temporally controlled. The processing chamber can be part of a multi-chamber substrate processing system.

公开(公告)号：US20140273530A1

公开(公告)日：2014-09-18

申请号：US14212425

申请日：2014-03-14

申请人： Victor Nguyen ,  Isabelita Roflox ,  Mihaela Balseanu ,  Li-Qun Xia ,  Heng Pan ,  Wei Liu ,  Malcolm J. Bevan ,  Christopher S. Olsen ,  Johanes F. Swenberg

发明人： Victor Nguyen ,  Isabelita Roflox ,  Mihaela Balseanu ,  Li-Qun Xia ,  Heng Pan ,  Wei Liu ,  Malcolm J. Bevan ,  Christopher S. Olsen ,  Johanes F. Swenberg

IPC分类号： H01L21/02

CPC分类号： H01L21/0217 ,  C23C16/045 ,  C23C16/345 ,  C23C16/45542 ,  C23C16/56 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02329 ,  H01L21/0234 ,  H01L21/02348 ,  H01L29/7843

摘要： Provided are methods post deposition treatment of films comprising SiN. Certain methods pertain to providing a film comprising SiN; and exposing the film to an inductively coupled plasma, capacitively coupled plasma or a microwave plasma to provide a treated film with a modulated film stress and/or wet etch rate in dilute HF. Certain other methods comprise depositing a PEALD SiN film followed by exposure to a plasma nitridation process or a UV treatment to provide a treated film.

摘要翻译： 提供了沉积处理包括SiN的膜的方法。 某些方法涉及提供包含SiN的膜; 并将该膜暴露于电感耦合等离子体，电容耦合等离子体或微波等离子体，以在稀HF中提供具有调制薄膜应力和/或湿蚀刻速率的处理薄膜。 某些其它方法包括沉积PEALD SiN膜，然后暴露于等离子体氮化处理或UV处理以提供经处理的膜。

公开(公告)号：US20130333923A1

公开(公告)日：2013-12-19

申请号：US13495545

申请日：2012-06-13

申请人： Mihaela Balseanu ,  Stephan A. Cohen ,  Alfred Grill ,  Thomas J. Haigh, JR. ,  Son V. Nguyen ,  Mei-Yee Shek ,  Hosadurga Shobha ,  Li-Qun Xia

发明人： Mihaela Balseanu ,  Stephan A. Cohen ,  Alfred Grill ,  Thomas J. Haigh, JR. ,  Son V. Nguyen ,  Mei-Yee Shek ,  Hosadurga Shobha ,  Li-Qun Xia

IPC分类号： C23C16/34 ,  H05K1/02

CPC分类号： C23C16/345 ,  C23C16/56 ,  H01L21/4803 ,  H05K1/0298 ,  Y10T428/24975

摘要： A layer of silicon nitride having a thickness from 0.5 nanometers to 2.4 nanometers is deposited on a substrate. A plasma nitridation process is carried out on the layer. These steps are repeated for a plurality of additional layers of silicon nitride, until a predetermined thickness is attained. Such steps can be used to provide a multilayer silicon nitride dielectric formed on a substrate having an upper surface of dielectric material with Cu and other conductors embedded within, and a plurality of steps. The multilayer silicon nitride dielectric has a plurality of individual layers each having a thickness from 0.5 nanometers to 2.4 nanometers, and the multilayer silicon nitride dielectric conformally covers the steps of the substrate with a conformality of at least seventy percent. A multilayer silicon nitride dielectric, and a multilevel back end of line interconnect wiring structure using same, are also provided.

摘要翻译： 将厚度为0.5纳米至2.4纳米的氮化硅层沉积在基底上。 在层上进行等离子体氮化处理。 对于多个附加氮化硅层重复这些步骤，直到达到预定厚度。 可以使用这样的步骤来提供形成在具有介电材料的上表面的衬底上的多层氮化硅电介质，其中Cu和其它导体嵌入其中并且多个步骤。 多层氮化硅电介质具有各自具有0.5纳米至2.4纳米厚度的多个单独层，多层氮化硅电介质保形地覆盖具有至少百分之七十的保形度的基底的步骤。 还提供了多层氮化硅电介质，以及使用该多层氮化硅电介质的多层后端的布线结构。

公开(公告)号：US20130196078A1

公开(公告)日：2013-08-01

申请号：US13754771

申请日：2013-01-30

申请人： Joseph Yudovsky ,  Nag B. Patibandla ,  Pravin K. Narwankar ,  Li-Qun Xia ,  Toshiaki Fujita ,  Ralf Hofmann ,  Jeonghoon Oh ,  Srinivas Satya ,  Banqiu Wu

发明人： Joseph Yudovsky ,  Nag B. Patibandla ,  Pravin K. Narwankar ,  Li-Qun Xia ,  Toshiaki Fujita ,  Ralf Hofmann ,  Jeonghoon Oh ,  Srinivas Satya ,  Banqiu Wu

IPC分类号： C23C16/458

CPC分类号： C23C16/4584 ,  C23C16/45519 ,  C23C16/45551 ,  C23C16/54 ,  H01L21/67742

摘要： A substrate processing system for processing multiple substrates is provided and generally includes at least one substrate processing platform and at least one substrate staging platform. The substrate processing platform includes a rotary track system capable of supporting multiple substrate support assemblies and continuously rotating the substrate support assemblies, each carrying a substrate thereon. Each substrate is positioned on a substrates support assembly disposed on the rotary track system and being processed through at least one shower head station and at least one buffer station, which are positioned atop the rotary track system of the substrate processing platform. Multiple substrates disposed on the substrate support assemblies are processed in and out the substrate processing platform. The substrate staging platform includes at least one dual-substrate processing station, each dual-substrate processing station includes two substrate support assemblies for supporting two substrates thereon.

摘要翻译： 提供了用于处理多个基板的基板处理系统，并且通常包括至少一个基板处理平台和至少一个基板分段平台。 基板处理平台包括能够支撑多个基板支撑组件并且连续旋转基板支撑组件的旋转轨道系统，每个基板支撑组件在其上承载基板。 每个基板定位在设置在旋转轨道系统上的基板支撑组件上，并且通过位于基板处理平台的旋转轨道系统顶部的至少一个喷头站和至少一个缓冲站进行处理。 设置在基板支撑组件上的多个基板在基板处理平台内进出处理。 衬底分级平台包括至少一个双衬底处理站，每个双衬底处理站包括用于在其上支撑两个衬底的两个衬底支撑组件。

公开(公告)号：US20130189841A1

公开(公告)日：2013-07-25

申请号：US13354939

申请日：2012-01-20

申请人： Mihaela Balseanu ,  Li-Qun Xia ,  Derek R. Witty ,  Thomas H. Osterheld ,  Christopher Heung-Gyun Lee ,  William H. McClintock

发明人： Mihaela Balseanu ,  Li-Qun Xia ,  Derek R. Witty ,  Thomas H. Osterheld ,  Christopher Heung-Gyun Lee ,  William H. McClintock

IPC分类号： H01L21/306

CPC分类号： H01L21/02126 ,  H01L21/02167 ,  H01L21/02274 ,  H01L21/31053 ,  H01L21/823807 ,  H01L29/66545 ,  H01L29/7843

摘要： A method for forming an integrated circuit is provided. In one embodiment, the method includes forming a stop layer comprising carbon doped silicon nitride on a gate region on a substrate, the gate region having a poly gate and one or more spacers formed adjacent the poly gate, forming a dielectric layer on the stop layer, and removing a portion of the dielectric layer above the gate region using a CMP process, wherein the stop layer is a strain inducing layer having a CMP removal rate that is less than the CMP removal rate of the dielectric layer and equal to or less than the CMP removal rate of the one or more spacers.

摘要翻译： 提供一种用于形成集成电路的方法。 在一个实施例中，该方法包括在衬底上的栅极区域上形成包含碳掺杂氮化硅的阻挡层，栅极区域具有多晶硅栅极和与多晶硅栅极相邻形成的一个或多个间隔区，在阻挡层上形成电介质层 并且使用CMP工艺去除所述栅极区域上方的所述电介质层的一部分，其中所述阻挡层是具有小于所述介电层的CMP去除速率的CMP去除速率的应变诱导层，并且等于或小于 一个或多个间隔物的CMP去除速率。

公开(公告)号：US08389376B2

公开(公告)日：2013-03-05

申请号：US12714865

申请日：2010-03-01

申请人： Alexandros T. Demos ,  Li-Qun Xia ,  Bok Hoen Kim ,  Derek R. Witty ,  Hichem M'Saad

发明人： Alexandros T. Demos ,  Li-Qun Xia ,  Bok Hoen Kim ,  Derek R. Witty ,  Hichem M'Saad

IPC分类号： H01L21/76

CPC分类号： H01L21/7682 ,  C23C16/401 ,  C23C16/56 ,  H01L21/02115 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02351 ,  H01L21/02362 ,  H01L21/3146 ,  H01L21/31633 ,  H01L21/31695 ,  H01L21/76811 ,  H01L21/76835 ,  H01L2221/1047 ,  Y10S438/931

摘要： Methods are provided for forming a structure that includes an air gap. In one embodiment, a method is provided for forming a damascene structure including depositing a porous low dielectric constant layer by a method including reacting an organosilicon compound and a porogen-providing precursor, depositing a porogen-containing material, and removing at least a portion of the porogen-containing material, depositing an organic layer on the porous low dielectric constant layer by reacting the porogen-providing precursor, forming a feature definition in the organic layer and the porous low dielectric constant layer, filing the feature definition with a conductive material therein, depositing a mask layer on the organic layer and the conductive material disposed in the feature definition, forming apertures in the mask layer to expose the organic layer, removing a portion or all of the organic layer through the apertures, and forming an air gap adjacent the conductive material.

摘要翻译： 提供了用于形成包括气隙的结构的方法。 在一个实施方案中，提供了一种用于形成镶嵌结构的方法，包括通过包括使有机硅化合物和致孔剂提供前体反应的方法沉积多孔低介电常数层，沉积含致孔剂的材料，以及除去至少一部分 含致孔剂的材料，通过使造孔剂提供前体反应，在有机层中形成特征定义和多孔低介电常数层，在多孔低介电常数层上沉积有机层，用导电材料填充特征定义 在有机层上沉积掩模层和设置在特征定义中的导电材料，在掩模层中形成孔以暴露有机层，通过孔去除部分或全部有机层，并形成相邻的气隙 导电材料。

公开(公告)号：US08143174B2

公开(公告)日：2012-03-27

申请号：US12013232

申请日：2008-01-11

申请人： Li-Qun Xia ,  Frederic Gaillard ,  Ellie Yieh ,  Tian H. Lim

发明人： Li-Qun Xia ,  Frederic Gaillard ,  Ellie Yieh ,  Tian H. Lim

IPC分类号： H01L21/26

CPC分类号： H01L21/02126 ,  C23C16/0218 ,  C23C16/401 ,  C23C16/56 ,  H01L21/02071 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02312 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/3105 ,  H01L21/3146 ,  H01L21/31604 ,  H01L21/31612 ,  H01L21/31633 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76837 ,  Y10S438/931

摘要： A method for providing a dielectric film having enhanced adhesion and stability. The method includes a post deposition treatment that densifies the film in a reducing atmosphere to enhance stability if the film is to be cured ex-situ. The densification generally takes place in a reducing environment while heating the substrate. The densification treatment is particularly suitable for silicon-oxygen-carbon low dielectric constant films that have been deposited at low temperature.

摘要翻译： 一种用于提供具有增强的粘合性和稳定性的电介质膜的方法。 该方法包括在还原气氛中使膜致密化的后沉积处理，以提高如果该膜不原位固化的稳定性。 致密化通常在还原环境中进行，同时加热基底。 致密化处理特别适用于在低温下沉积的硅 - 氧 - 碳低介电常数膜。

公开(公告)号：US07964442B2

公开(公告)日：2011-06-21

申请号：US11869416

申请日：2007-10-09

申请人： Huiwen Xu ,  Yijun Liu ,  Li-Qun Xia ,  Derek R. Witty ,  Hichem M'Saad

发明人： Huiwen Xu ,  Yijun Liu ,  Li-Qun Xia ,  Derek R. Witty ,  Hichem M'Saad

IPC分类号： H01L51/40

CPC分类号： H01L21/02205 ,  C23C16/22 ,  C23C16/505 ,  H01L21/02112 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/3121 ,  H01L21/3148 ,  H01L21/3185

摘要： The present invention generally provides a method for forming a dielectric barrier with lowered dielectric constant, improved etching resistivity and good barrier property. One embodiment provides a method for processing a semiconductor substrate comprising flowing a precursor to a processing chamber, wherein the precursor comprises silicon-carbon bonds and carbon-carbon bonds, and generating a low density plasma of the precursor in the processing chamber to form a dielectric barrier film having carbon-carbon bonds on the semiconductor substrate, wherein the at least a portion of carbon-carbon bonds in the precursor is preserved in the low density plasma and incorporated in the dielectric barrier film.

摘要翻译： 本发明通常提供一种形成具有降低的介电常数，改进的蚀刻电阻率和良好的阻挡性能的介电阻挡层的方法。 一个实施例提供了一种用于处理半导体衬底的方法，包括将前体流入处理室，其中前体包含硅 - 碳键和碳 - 碳键，并在处理室中产生前体的低密度等离子体以形成电介质 在半导体衬底上具有碳 - 碳键的阻挡膜，其中前体中的至少一部分碳 - 碳键保存在低密度等离子体中并且并入介电阻挡膜中。