公开(公告)号：US20170208684A1

公开(公告)日：2017-07-20

申请号：US15476235

申请日：2017-03-31

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Ralf Otremba

IPC: H05K1/03 ,  H05K1/11 ,  H05K3/00 ,  H05K3/02 ,  H05K1/02 ,  H05K3/40

CPC classification number: H05K1/036 ,  H05K1/0203 ,  H05K1/032 ,  H05K1/0373 ,  H05K1/115 ,  H05K3/0014 ,  H05K3/007 ,  H05K3/0094 ,  H05K3/02 ,  H05K3/105 ,  H05K3/4038 ,  H05K3/4626 ,  H05K2201/0104 ,  H05K2201/0129 ,  H05K2201/0215 ,  H05K2201/0224 ,  H05K2201/0281 ,  H05K2203/107 ,  H05K2203/1136 ,  Y10T29/49126 ,  Y10T428/24909

Abstract: A printed circuit board includes an electrically conductive layer and a dielectric layer including a polymer. The polymer includes at least one of a carbon layer structure and a carbon-like layer structure.

公开(公告)号：US20170186663A1

公开(公告)日：2017-06-29

申请号：US15381155

申请日：2016-12-16

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Peter Irsigler ,  Joachim Mahler ,  Guenther Ruhl ,  Hans-Joachim Schulze ,  Markus Zundel

IPC: H01L23/367 ,  H01L29/40 ,  H01L29/10 ,  H01L29/423 ,  H01L29/417

CPC classification number: H01L23/3672 ,  B82Y30/00 ,  H01L23/3677 ,  H01L23/373 ,  H01L23/3737 ,  H01L23/4275 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/405 ,  H01L29/407 ,  H01L29/417 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7813 ,  Y10S977/742 ,  Y10S977/753

Abstract: A semiconductor device includes a drift structure formed in a semiconductor body. The drift structure forms a first pn junction with a body zone of a transistor cell. A gate structure extends from a first surface of the semiconductor body into the drift structure. A heat sink structure extends from the first surface into the drift structure. A thermal conductivity of the heat sink structure is greater than a thermal conductivity of the gate structure and/or a thermal capacity of the heat sink structure is greater than a thermal capacity of the gate structure.

公开(公告)号：US09648735B2

公开(公告)日：2017-05-09

申请号：US14729158

申请日：2015-06-03

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Ralf Otremba

IPC: H05K1/03 ,  H05K3/00 ,  H05K1/11 ,  H05K3/10 ,  H05K3/46

CPC classification number: H05K1/036 ,  H05K1/0203 ,  H05K1/032 ,  H05K1/0373 ,  H05K1/115 ,  H05K3/0014 ,  H05K3/007 ,  H05K3/0094 ,  H05K3/02 ,  H05K3/105 ,  H05K3/4038 ,  H05K3/4626 ,  H05K2201/0104 ,  H05K2201/0129 ,  H05K2201/0215 ,  H05K2201/0224 ,  H05K2201/0281 ,  H05K2203/107 ,  H05K2203/1136 ,  Y10T29/49126 ,  Y10T428/24909

Abstract: A printed circuit board includes an electrically conductive layer and a dielectric layer including a polymer, wherein the polymer includes metallic particles.

公开(公告)号：US20170082502A1

公开(公告)日：2017-03-23

申请号：US15369057

申请日：2016-12-05

Applicant: Infineon Technologies AG

Inventor： Christian Kegler ,  Johannes Georg Laven ,  Hans-Joachim Schulze ,  Guenther Ruhl ,  Joachim Mahler

IPC: G01K7/16 ,  H01L29/20 ,  H01L29/16

Abstract: Temperature sensor devices and corresponding methods are provided. A temperature sensor may include a first layer being essentially non-conductive in a temperature range and a second layer having a varying resistance in the temperature range.

公开(公告)号：US20160211226A1

公开(公告)日：2016-07-21

申请号：US14987820

申请日：2016-01-05

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Joachim Mahler ,  Ivan Nikitin

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/48 ,  H01L21/56 ,  H01L23/495 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L21/4825 ,  H01L21/4832 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49548 ,  H01L23/49582 ,  H01L23/49586 ,  H01L24/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In various embodiments, an integrated circuit is provided. The integrated circuit may include a semiconductor chip and an electrically conductive composite material fixed to the semiconductor chip, wherein the electrically conductive composite material may include a metal, and wherein a coefficient of thermal expansion (CTE) value of the electrically conductive composite material may be lower than the CTE value of the metal.

Abstract translation: 在各种实施例中，提供集成电路。 集成电路可以包括固定到半导体芯片的半导体芯片和导电复合材料，其中导电复合材料可以包括金属，并且其中导电复合材料的热膨胀系数（CTE）值可以是 低于金属的CTE值。

公开(公告)号：US09397018B2

公开(公告)日：2016-07-19

申请号：US13742456

申请日：2013-01-16

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Juergen Schredl ,  Xaver Schloegel ,  Wolfram Hable ,  Manfred Mengel ,  Joachim Mahler ,  Khalil Hosseini

IPC: H01L23/373 ,  H01L23/29 ,  H01L21/56 ,  H01L23/31 ,  H01L23/06 ,  H01L23/495 ,  H01L23/00

CPC classification number: H01L23/29 ,  H01L21/56 ,  H01L23/06 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A chip arrangement is provided, the chip arrangement, including a carrier; at least one chip electrically connected to a carrier top side; an encapsulation material at least partially surrounding the at least one chip and the carrier top side, wherein the encapsulation material is formed on one or more lateral sides of the carrier; and a ceramic material disposed on a carrier bottom side, and on at least one side of the encapsulation material.

Abstract translation: 提供了芯片布置，芯片布置包括载体; 至少一个芯片电连接到载体顶侧; 至少部分地围绕所述至少一个芯片和所述载体顶侧的封装材料，其中所述封装材料形成在所述载体的一个或多个侧面上; 以及设置在载体底侧上的至少一个侧面上的陶瓷材料。

公开(公告)号：US20160163689A1

公开(公告)日：2016-06-09

申请号：US14959276

申请日：2015-12-04

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Christian Jaeger ,  Joachim Mahler ,  Daniel Pedone ,  Anton Prueckl ,  Hans-Joachim Schulze ,  Andre Schwagmann ,  Patrick Schwarz

IPC: H01L27/02 ,  H01L29/78

CPC classification number: H01L27/0255 ,  H01C7/04 ,  H01L29/7803 ,  H01L29/7805 ,  H01L29/7808 ,  H01L29/7813 ,  H01L45/00

Abstract: A semiconductor device includes a first load terminal electrically coupled to a source zone of a transistor cell. A gate terminal is electrically coupled to a gate electrode which is capacitively coupled to a body zone of the transistor cell. The source and body zones are formed in a semiconductor portion. A thermoresistive element is thermally connected to the semiconductor portion and is electrically coupled between the gate terminal and the first load terminal. Above a maximum operation temperature specified for the semiconductor device, an electric resistance of the thermoresistive element decreases by at least two orders of magnitude within a critical temperature span of at most 50 Kelvin.

Abstract translation: 半导体器件包括电耦合到晶体管单元的源极区的第一负载端子。 栅极端子电耦合到电容耦合到晶体管单元的体区的栅电极。 源区和体区形成在半导体部分中。 热电阻元件热连接到半导体部分，并且电连接在栅极端子和第一负载端子之间。 在对于半导体器件规定的最大工作温度之上，耐温元件的电阻在至多50开尔文的临界温度范围内降低至少两个数量级。

公开(公告)号：US20150359091A1

公开(公告)日：2015-12-10

申请号：US14729158

申请日：2015-06-03

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Ralf Otremba

IPC: H05K1/03 ,  H05K3/00 ,  H05K1/11

CPC classification number: H05K1/036 ,  H05K1/0203 ,  H05K1/032 ,  H05K1/0373 ,  H05K1/115 ,  H05K3/0014 ,  H05K3/007 ,  H05K3/0094 ,  H05K3/02 ,  H05K3/105 ,  H05K3/4038 ,  H05K3/4626 ,  H05K2201/0104 ,  H05K2201/0129 ,  H05K2201/0215 ,  H05K2201/0224 ,  H05K2201/0281 ,  H05K2203/107 ,  H05K2203/1136 ,  Y10T29/49126 ,  Y10T428/24909

Abstract: A printed circuit board includes an electrically conductive layer and a dielectric layer including a polymer, wherein the polymer includes metallic particles.

Abstract translation: 印刷电路板包括导电层和包括聚合物的介电层，其中聚合物包括金属颗粒。

公开(公告)号：US09171804B2

公开(公告)日：2015-10-27

申请号：US13681079

申请日：2012-11-19

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg ,  Khalil Hosseini ,  Joachim Mahler ,  Edward Fuergut

IPC: H01L21/58 ,  H01L21/78 ,  H01L23/538 ,  H01L23/00 ,  H01L23/495 ,  H01L21/56

CPC classification number: H01L23/5384 ,  H01L21/561 ,  H01L21/563 ,  H01L21/78 ,  H01L23/49513 ,  H01L23/49562 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/32245 ,  H01L2224/83191 ,  H01L2224/83194 ,  H01L2224/83203 ,  H01L2224/83207 ,  H01L2224/83439 ,  H01L2224/83455 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15747 ,  H01L2924/00

Abstract: A carrier and a semiconductor chip are provided. A connection layer is applied to a first main face of the semiconductor chip. The connection layer includes a plurality of depressions. A filler is applied to the connection layer or to the carrier. The semiconductor chip is attached to the carrier so that the connection layer is disposed between the semiconductor chip and the carrier. The semiconductor chip is affixed to the carrier.

Abstract translation: 提供载体和半导体芯片。 连接层被施加到半导体芯片的第一主面。 连接层包括多个凹陷。 将填料施加到连接层或载体上。 将半导体芯片附着到载体上，使得连接层设置在半导体芯片和载体之间。 半导体芯片固定在载体上。

公开(公告)号：US09159701B2

公开(公告)日：2015-10-13

申请号：US14028577

申请日：2013-09-17

Applicant: Infineon Technologies AG

Inventor： Khalil Hosseini ,  Joachim Mahler ,  Franz-Peter Kalz ,  Joachim Voelter ,  Ralf Wombacher

IPC: H01L23/52 ,  H01L21/60 ,  H01L23/48 ,  H01L21/50 ,  H01L21/56 ,  H01L23/00 ,  H01L23/495 ,  H01L23/492 ,  H01L23/498

CPC classification number: H01L25/0655 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/492 ,  H01L23/49558 ,  H01L23/49575 ,  H01L23/49586 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83095 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/8382 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/82 ,  H01L2224/83

Abstract: A method of manufacturing a chip package is provided. The method may include electrically contacting at least one first chip, the first chip including a first side and a second side opposite the first side, with its second side to an electrically conductive carrier. An insulating layer is formed over at least a part of the electrically conductive carrier and over at least a part of the first side of the chip. At least one second chip is arranged over the insulating layer. An encapsulating material is formed over the first chip and the second chip. Electrical contacts are formed through the encapsulation material to at least one contact of the at least one first chip and to at least one contact of the at least one second chip.

Abstract translation: 提供了一种制造芯片封装的方法。 该方法可以包括电接触至少一个第一芯片，第一芯片包括第一侧和与第一侧相对的第二侧，其第二侧为导电载体。 绝缘层形成在导电载体的至少一部分上并且在芯片的第一侧的至少一部分上方。 至少一个第二芯片布置在绝缘层上。 在第一芯片和第二芯片上形成封装材料。 电触头通过封装材料形成至少一个第一芯片和至少一个第二芯片的至少一个触点的至少一个触点。