公开(公告)号：US06424038B1

公开(公告)日：2002-07-23

申请号：US09812029

申请日：2001-03-19

申请人： Tien-I Bao ,  Syun-Ming Jang

发明人： Tien-I Bao ,  Syun-Ming Jang

IPC分类号： H01L2348

CPC分类号： H01L21/76832 ,  H01L21/7681 ,  H01L23/3192 ,  H01L23/49894 ,  H01L23/53238 ,  H01L23/53271 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/00

摘要： Within both a microelectronic conductor structure and a method for forming the microelectronic conductor structure there is employed a silicon carbide layer having formed thereupon a silicon nitride layer in turn having formed thereupon a patterned low dielectric constant dielectric layer in turn having formed interposed between its patterns a patterned conductor layer. Within both the microelectronic conductor structure and the method for forming the microelectronic conductor structure, by employing the silicon carbide layer having formed thereupon the silicon nitride layer in turn having formed thereupon the patterned low dielectric constant dielectric layer, the microelectronic conductor structure is formed with enhanced adhesion and attenuated electrical leakage.

摘要翻译： 在微电子导体结构和形成微电子导体结构的方法中，都采用在其上形成氮化硅层的碳化硅层，依次形成图案化的低介电常数介电层，其间形成有介于其图案a 图案导体层。 在微电子导体结构和形成微电子导体结构的方法中，通过使用其上形成的碳化硅层依次形成有图案化的低介电常数介电层的氮化硅层，微电子导体结构形成有增强的 粘附和减弱漏电。

公开(公告)号：US06350694B1

公开(公告)日：2002-02-26

申请号：US09814038

申请日：2001-03-22

申请人： Weng Chang ,  Tien-I Bao ,  Syun-Ming Jang

发明人： Weng Chang ,  Tien-I Bao ,  Syun-Ming Jang

IPC分类号： H01L21302

CPC分类号： G11C11/406 ,  G11C11/404 ,  G11C11/40603 ,  G11C11/4096 ,  H01L21/02074 ,  H01L21/31055 ,  H01L21/31058 ,  H01L21/3212 ,  H01L21/76819 ,  H01L21/7684

摘要： A new plasma etch back is provided that is applied to the surface of a low-k dielectric after the process of CMP of a copper surface has been completed. The copper surface is the surface of interconnect metal, the interconnect metal is embedded in the layer of low-k dielectric.

摘要翻译： 提供了一种新的等离子体回蚀，其在铜表面的CMP处理已经完成之后被施加到低k电介质的表面。 铜表面是互连金属的表面，互连金属嵌入在低k电介质层中。

公开(公告)号：US20220155254A1

公开(公告)日：2022-05-19

申请号：US16951751

申请日：2020-11-18

申请人： Tien-I Bao

发明人： Tien-I Bao

IPC分类号： G01N27/416 ,  G01N33/18 ,  G01F23/00 ,  G01N1/14

摘要： A seawater alkalinity detection system includes a mainframe, a container, and an external apparatus. The mainframe includes a pump motor, a PH value detecting pole, a dosing delivery port, a seawater delivery port, a KH to PH converter output port, a power supply port, a network connection control unit, a detecting operation unit, and a water level controller. The container defines a first detection space containing a contrast liquid, a second detection space containing a reference liquid, and a receiving space accommodating the contrast liquid that is tested. Thus, the seawater alkalinity detection system that automatically detects the KH value of the reference liquid in the seawater storage bucket, and automatically controls the dosing data to add the additive automatically to change the second PH value of the reference liquid in the seawater storage bucket, without having to add a medicinal liquid.

公开(公告)号：US09349595B2

公开(公告)日：2016-05-24

申请号：US13546800

申请日：2012-07-11

申请人： Cheng-Hsiung Tsai ,  Chung-Ju Lee ,  Hsin-Chieh Yao ,  Tien-I Bao

发明人： Cheng-Hsiung Tsai ,  Chung-Ju Lee ,  Hsin-Chieh Yao ,  Tien-I Bao

IPC分类号： H01L21/311 ,  H01L21/033 ,  H01L21/768 ,  H01L21/02

CPC分类号： H01L21/0337 ,  H01L21/02115 ,  H01L21/31144 ,  H01L21/76816

摘要： Methods of manufacturing semiconductor devices are disclosed. In one embodiment, a material layer is formed over a workpiece. The workpiece includes a first portion, a second portion, and a hard mask disposed between the first portion and the second portion. The material layer is patterned, and first spacers are formed on sidewalls of the patterned material layer. The patterned material layer is removed, and the second portion of the workpiece is patterned using the first spacers as an etch mask. The first spacers are removed, and second spacers are formed on sidewalls of the patterned second portion of the workpiece. The patterned second portion of the workpiece is removed, and the hard mask of the workpiece is patterned using the second spacers as an etch mask. The first portion of the workpiece is patterned using the hard mask as an etch mask.

摘要翻译： 公开了制造半导体器件的方法。 在一个实施例中，材料层形成在工件上。 工件包括设置在第一部分和第二部分之间的第一部分，第二部分和硬掩模。 图案化材料层，并且在图案化材料层的侧壁上形成第一间隔物。 去除图案化的材料层，并且使用第一间隔件作为蚀刻掩模来对工件的第二部分进行图案化。 去除第一间隔物，并且在工件的图案化第二部分的侧壁上形成第二间隔物。 去除工件的图案化的第二部分，并且使用第二间隔件作为蚀刻掩模来对工件的硬掩模进行图案化。 使用硬掩模作为蚀刻掩模来对工件的第一部分进行图案化。

公开(公告)号：US09036956B2

公开(公告)日：2015-05-19

申请号：US13399098

申请日：2012-02-17

申请人： Chun-Hao Tseng ,  Wan-Yu Lee ,  Hai-Ching Chen ,  Tien-I Bao

发明人： Chun-Hao Tseng ,  Wan-Yu Lee ,  Hai-Ching Chen ,  Tien-I Bao

IPC分类号： G02B6/12 ,  G02B6/138 ,  F21V8/00 ,  G02B6/42

CPC分类号： G02B6/12004 ,  G02B6/0083 ,  G02B6/132 ,  G02B6/136 ,  G02B6/138 ,  G02B6/4214 ,  G02B2006/12061 ,  G02B2006/12104 ,  G02B2006/12121 ,  G02B2006/12176

摘要： A method of fabricating a waveguide device is disclosed. The method includes providing a substrate having an elector-interconnection region and a waveguide region and forming a patterned dielectric layer and a patterned redistribution layer (RDL) over the substrate in the electro-interconnection region. The method also includes bonding the patterned RDL to a vertical-cavity surface-emitting laser (VCSEL) through a bonding stack. A reflecting-mirror trench is formed in the substrate in the waveguide region, and a reflecting layer is formed over a reflecting-mirror region inside the waveguide region. The method further includes forming and patterning a bottom cladding layer in a wave-tunnel region inside the waveguide region and forming and patterning a core layer and a top cladding layer in the waveguide region.

摘要翻译： 公开了一种制造波导器件的方法。 该方法包括提供具有选通互连区域和波导区域的衬底，并且在电互连区域中的衬底上形成图案化电介质层和图案化再分配层（RDL）。 该方法还包括通过结合堆叠将图案化的RDL结合到垂直腔表面发射激光器（VCSEL）。 在波导区域的基板上形成反射镜沟槽，反射层形成在波导区域内的反射镜区域的上方。 该方法还包括在波导区域内的波通道区域中形成和图案化底包层，并且在波导区域中形成和图案化芯层和顶包层。

公开(公告)号：US09029171B2

公开(公告)日：2015-05-12

申请号：US13531738

申请日：2012-06-25

申请人： Tsung-Min Huang ,  Chung-Ju Lee ,  Tien-I Bao

发明人： Tsung-Min Huang ,  Chung-Ju Lee ,  Tien-I Bao

IPC分类号： H01L21/00 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/768

CPC分类号： H01L23/5329 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02321 ,  H01L21/3105 ,  H01L21/76814 ,  H01L21/76826 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure relates to a structure and method to create a self-repairing dielectric material for semiconductor device applications. A porous dielectric material is deposited on a substrate, and exposed with treating agent particles such that the treating agent particles diffuse into the dielectric material. A dense non-porous cap is formed above the dielectric material which encapsulates the treating agent particles within the dielectric material. The dielectric material is then subjected to a process which creates damage to the dielectric material. A chemical reaction is initiated between the treating agent particles and the damage, repairing the damage. A gradient concentration resulting from the consumption of treating agent particles by the chemical reaction promotes continuous diffusion the treating agent particles towards the damaged region of the dielectric material, continuously repairing the damage.

摘要翻译： 本公开涉及一种用于为半导体器件应用创建自修复电介质材料的结构和方法。 将多孔电介质材料沉积在基底上，并用处理剂颗粒暴露，使得处理剂颗粒扩散到电介质材料中。 在电介质材料上形成致密的无孔盖，其将电介质材料中的处理剂颗粒封装起来。 然后对电介质材料进行对电介质材料造成损伤的工艺。 在处理剂颗粒和损坏之间引发化学反应，修复损坏。 通过化学反应消耗处理剂颗粒而产生的梯度浓度促使处理剂颗粒朝向电介质材料的损坏区域的连续扩散，连续地修复损伤。

公开(公告)号：US08889544B2

公开(公告)日：2014-11-18

申请号：US13028889

申请日：2011-02-16

申请人： Yung-Hsu Wu ,  Hsin-Hsien Lu ,  Tien-I Bao ,  Shau-Lin Shue

发明人： Yung-Hsu Wu ,  Hsin-Hsien Lu ,  Tien-I Bao ,  Shau-Lin Shue

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L21/311 ,  H01L23/532 ,  H01L21/02 ,  H01L21/321

CPC分类号： H01L21/3212 ,  H01L21/02203 ,  H01L21/02348 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/7684 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

摘要： The disclosure provides mechanisms of performing metal chemical-mechanical polishing (CMP) without significant loss of copper and a dielectric film of damascene structures. The mechanisms use a metal CMP stop layer made of a low-k dielectric film with a porogen, which significantly reduces the removal rate of the metal CMP stop layer by metal CMP. The metal CMP stop layer is converted into a porous low-k dielectric film after a cure (or curing) to remove or convert the porogen. The low-k value, such as equal to or less than about 2.6, of the metal CMP stop layer makes the impact of using of the metal CMP stop layer on RC delay from minimum to none. Further the CMP stop layer protects the porous low-k dielectric film underneath from exposure to water, organic compounds, and mobile ions in the CMP slurry.

摘要翻译： 本公开提供了进行金属化学机械抛光（CMP）而不显着损失铜和镶嵌结构的介电膜的机理。 这些机制使用由具有致孔剂的低k电介质膜制成的金属CMP停止层，这显着地降低了通过金属CMP的金属CMP停止层的去除速率。 在固化（或固化）之后，将金属CMP停止层转化为多孔低k电介质膜以去除或转化致孔剂。 金属CMP停止层的低k值（例如等于或小于约2.6）使得金属CMP停止层的使用对RC延迟的影响从最小到无。 此外，CMP停止层保护下面的多孔低k电介质膜不暴露于CMP浆料中的水，有机化合物和移动离子。

公开(公告)号：US08735278B2

公开(公告)日：2014-05-27

申请号：US13550951

申请日：2012-07-17

申请人： Ming Han Lee ,  Hai-Ching Chen ,  Hsiang-Huan Lee ,  Tien-I Bao ,  Chi-Lin Teng

发明人： Ming Han Lee ,  Hai-Ching Chen ,  Hsiang-Huan Lee ,  Tien-I Bao ,  Chi-Lin Teng

IPC分类号： H01L21/4763

CPC分类号： H01L23/53238 ,  H01L21/76834 ,  H01L21/76867 ,  H01L21/76885 ,  H01L21/76897 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure is directed to a method of manufacturing an interconnect structure in which a low-k dielectric layer is formed over a semiconductor substrate followed by formation of a copper or copper alloy layer over the low-k dielectric layer. The copper or copper alloy layer is patterned and etched to form a copper body having recesses, which are then filled with a low-k dielectric material. The method allows for formation of a damascene structures without encountering the various problems presented by non-planar features and by porus low-K dielectric damage.

摘要翻译： 本公开涉及一种制造互连结构的方法，其中在半导体衬底上形成低k电介质层，然后在低k电介质层上形成铜或铜合金层。 铜或铜合金层被图案化和蚀刻以形成具有凹部的铜体，然后填充有低k电介质材料。 该方法允许形成镶嵌结构，而不会遇到由非平面特征和孔隙低K电介质损伤所呈现的各种问题。

公开(公告)号：US20140065818A1

公开(公告)日：2014-03-06

申请号：US13599764

申请日：2012-08-30

申请人： Chih Wei Lu ,  Chung-Ju Lee ,  Hsiang-Huan Lee ,  Tien-I Bao

发明人： Chih Wei Lu ,  Chung-Ju Lee ,  Hsiang-Huan Lee ,  Tien-I Bao

IPC分类号： H01L21/768

CPC分类号： H01L21/76852 ,  H01L21/7682 ,  H01L21/76885 ,  H01L23/53233 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A sacrifice layer (SL) is formed and patterned on the substrate. The patterned SL has a plurality of openings. The method also includes forming a metal layer in the openings and then removing the patterned SL to laterally expose at least a portion of the metal layer to form a metal feature, which has a substantial same profile as the opening. A dielectric layer is deposited on sides of the metal feature.

摘要翻译： 公开了制造半导体集成电路（IC）的方法。 该方法包括提供基板。 牺牲层（SL）在衬底上形成并图案化。 图案化SL具有多个开口。 该方法还包括在开口中形成金属层，然后移除图案化的SL以横向暴露金属层的至少一部分以形成具有与开口基本相同的轮廓的金属特征。 电介质层沉积在金属特征的侧面上。

公开(公告)号：US20060211240A1

公开(公告)日：2006-09-21

申请号：US11084494

申请日：2005-03-18

申请人： Chung Chi ,  Tien-I Bao ,  Syun-Ming Jang ,  Shou-Yi Chang

发明人： Chung Chi ,  Tien-I Bao ,  Syun-Ming Jang ,  Shou-Yi Chang

IPC分类号： H01L21/4763 ,  H01L21/31

CPC分类号： H01L21/3122 ,  H01L21/02123 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/312 ,  H01L21/3124 ,  H01L21/3125 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/31629 ,  H01L21/31695 ,  H01L21/3212 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76835

摘要： A method for enhancing adhesion between adjacent dielectric layers, particularly in the formation of trenches and vias in the layers during the fabrication of semiconductor integrated circuits on wafer substrates. The method may include providing a via dielectric layer on a substrate above a metal conductive layer in the substrate, providing an adhesive layer on the via dielectric layer, providing a trench dielectric layer on the adhesive layer, etching a via in the via dielectric layer, etching a trench in the trench dielectric layer, filling the via and trench with a metal filling layer, and planarizing the filling layer. The adhesive layer between the via dielectric layer and the trench dielectric layer prevents CMP-induced peeling during the planarization step, and cracking of the layers during the package step.

摘要翻译： 一种用于增强相邻电介质层之间的粘附性的方法，特别是在晶片衬底上制造半导体集成电路期间在层中形成沟槽和通孔的方法。 该方法可以包括在衬底上的金属导电层上方的衬底上提供通孔电介质层，在通孔电介质层上提供粘合剂层，在粘合剂层上提供沟槽电介质层，蚀刻通孔电介质层中的通孔， 蚀刻沟槽电介质层中的沟槽，用金属填充层填充通孔和沟槽，并平坦化填充层。 通孔电介质层和沟槽电介质层之间的粘合剂层防止了在平坦化步骤期间的CMP引起的剥离以及在封装步骤期间层的破裂。