Bonded structure employing metal semiconductor alloy bonding
    91.
    发明授权
    Bonded structure employing metal semiconductor alloy bonding 有权
    使用金属半导体合金结合的结合结构

    公开(公告)号:US08841777B2

    公开(公告)日:2014-09-23

    申请号:US12685954

    申请日:2010-01-12

    摘要: Vertical stacks of a metal portion and a semiconductor portion formed on a first substrate are brought into physical contact with vertical stacks of a metal portion and a semiconductor portion formed on a second substrate. Alternately, vertical stacks of a metal portion and a semiconductor portion formed on a first substrate are brought into physical contact with metal portions formed on a second substrate. The assembly of the first and second substrates is subjected to an anneal at a temperature that induces formation of a metal semiconductor alloy derived from the semiconductor portions and the metal portions. The first substrate and the second substrate are bonded through metal semiconductor alloy portions that adhere to the first and second substrates.

    摘要翻译: 形成在第一基板上的金属部分和半导体部分的垂直叠层与形成在第二基板上的金属部分和半导体部分的垂直叠层物理接触。 或者,形成在第一基板上的金属部分和半导体部分的垂直堆叠与形成在第二基板上的金属部分物理接触。 在引起由半导体部分和金属部分衍生的金属半导体合金的形成的温度下对第一和第二基板的组装进行退火。 第一基板和第二基板通过粘附到第一和第二基板的金属半导体合金部分接合。

    Sidewalls of electroplated copper interconnects
    92.
    发明授权
    Sidewalls of electroplated copper interconnects 有权
    电镀铜互连的侧壁

    公开(公告)号:US08791005B2

    公开(公告)日:2014-07-29

    申请号:US13525823

    申请日:2012-06-18

    IPC分类号: H01L23/532

    摘要: A structure formed in an opening having a substantially vertical sidewall defined by a non-metallic material and having a substantially horizontal bottom defined by a conductive pad, the structure including a diffusion barrier covering the sidewall and a fill composed of conductive material. The structure including a first intermetallic compound separating the diffusion barrier from the conductive material, the first intermetallic compound comprises an alloying material and the conductive material, and is mechanically bound to the conductive material, the alloying material is at least one of the materials selected from the group of chromium, tin, nickel, magnesium, cobalt, aluminum, manganese, titanium, zirconium, indium, palladium, and silver; and a first high friction interface located between the diffusion barrier and the first intermetallic compound and parallel to the sidewall of the opening, wherein the first high friction interface results in a mechanical bond between the diffusion barrier and the first intermetallic compound.

    摘要翻译: 一种形成在开口中的结构,其具有由非金属材料限定的基本上垂直的侧壁,并且具有由导电垫限定的基本上水平的底部,该结构包括覆盖侧壁的扩散阻挡层和由导电材料构成的填充物。 所述结构包括将所述扩散阻挡物与所述导电材料分离的第一金属间化合物,所述第一金属间化合物包括合金材料和所述导电材料,并且机械地结合到所述导电材料上,所述合金材料是选自以下的至少一种材料: 铬,锡,镍,镁,钴,铝,锰,钛,锆,铟,钯和银的组合; 以及位于所述扩散阻挡层和所述第一金属间化合物之间且平行于所述开口的侧壁的第一高摩擦界面,其中所述第一高摩擦界面导致所述扩散阻挡层和所述第一金属间化合物之间的机械结合。

    Method and structure of forming backside through silicon via connections
    95.
    发明授权
    Method and structure of forming backside through silicon via connections 有权
    通过连接通过硅形成背面的方法和结构

    公开(公告)号:US08709936B2

    公开(公告)日:2014-04-29

    申请号:US13562927

    申请日:2012-07-31

    IPC分类号: H01L21/00

    摘要: A method, and the resulting structure, to make a thinned substrate with backside redistribution wiring connected to through silicon vias of varying height. The method includes thinning a backside of a substrate to expose through silicon vias. Then a thick insulator stack, including an etch stop layer, is deposited and planarized. With a planar insulating surface in place, openings in the insulator stack can be formed by etching. The etch stop layer in the dielectric stack accommodates the differing heights vias. The etch stop is removed and a conductor having a liner is formed in the opening. The method gives a unique structure in which a liner around the bottom of the through silicon via remains in tact. Thus, the liner of the via and a liner of the conductor meet to form a double liner at the via/conductor junction.

    摘要翻译: 一种方法和所得到的结构,使得具有通过不同高度的硅通孔连接到背侧再分布布线的薄化基板。 该方法包括使衬底的背面变薄以通过硅通孔暴露。 然后沉积包括蚀刻停止层的厚的绝缘体堆叠并平坦化。 通过平面绝缘表面就可以通过蚀刻形成绝缘体堆叠中的开口。 电介质堆叠中的蚀刻停止层容纳不同的高度通孔。 去除蚀刻停止件,并且在开口中形成具有衬垫的导体。 该方法提供了一种独特的结构,其中通过硅通孔底部的衬垫仍然保持平衡。 因此,通孔的衬垫和导体的衬垫在通孔/导体结处相交以形成双衬垫。

    OPTIMIZED ANNULAR COPPER TSV
    100.
    发明申请
    OPTIMIZED ANNULAR COPPER TSV 有权
    优化的环形铜片TSV

    公开(公告)号:US20120326309A1

    公开(公告)日:2012-12-27

    申请号:US13167107

    申请日:2011-06-23

    IPC分类号: H01L23/48 H01L21/283

    摘要: The present disclosure provides a thermo-mechanically reliable copper TSV and a technique to form such TSV during BEOL processing. The TSV constitutes an annular trench which extends through the semiconductor substrate. The substrate defines the inner and outer sidewalls of the trench, which sidewalls are separated by a distance within the range of 5 to 10 microns. A conductive path comprising copper or a copper alloy extends within said trench from an upper surface of said first dielectric layer through said substrate. The substrate thickness can be 60 microns or less. A dielectric layer having interconnect metallization conductively connected to the conductive path is formed directly over said annular trench.

    摘要翻译: 本公开提供了热机械可靠的铜TSV和在BEOL处理期间形成这种TSV的技术。 TSV构成延伸穿过半导体衬底的环形沟槽。 衬底限定沟槽的内侧壁和外侧壁,该侧壁分隔5至10微米的距离。 包括铜或铜合金的导电路径从所述第一介电层的上表面通过所述衬底在所述沟槽内延伸。 基板厚度可以为60微米或更小。 具有导电连接到导电路径的互连金属化的电介质层直接形成在所述环形沟槽上。