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    GATE STACKS AND OHMIC CONTACTS FOR SIC DEVICES
    92.
    发明申请
    GATE STACKS AND OHMIC CONTACTS FOR SIC DEVICES 有权
    用于SIC设备的门盖和OHMIC联系

    公开(公告)号：US20150179438A1

    公开(公告)日：2015-06-25

    申请号：US14136271

    申请日：2013-12-20

    Applicant: Intermolecular, Inc.

    Inventor： Khaled Ahmed ,  Frank Greer ,  Raj Jammy

    IPC: H01L21/02 ,  H01L29/40

    CPC classification number: H01L21/02301 ,  C23C16/0227 ,  C23C16/56 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02307 ,  H01L21/02315 ,  H01L21/0234 ,  H01L21/0485 ,  H01L29/66068 ,  H01L29/78

    Abstract: SiC substrates are cleaned and provided to a process chamber. In-situ plasma surface treatments are applied to further clean the surface of the substrate. A dielectric interface layer is deposited in-situ to passivate the surface. Metal layers having a low work function are deposited above the dielectric interface layer. The stack is annealed at about 500C in forming gas to form low resistivity ohmic contacts to the SiC substrate. SiC substrates are cleaned and provided to a process chamber. In-situ plasma surface treatments are applied to further clean the surface of the substrate. A silicon oxide dielectric interface layer is deposited in-situ to passivate the surface. Optional plasma surface treatments are applied to further improve the performance of the silicon oxide dielectric interface layer. An aluminum oxide gate dielectric layer is deposited above the silicon oxide dielectric interface layer.

    Abstract translation: 将SiC衬底清洁并提供给处理室。 施加原位等离子体表面处理以进一步清洁基底的表面。 电介质界面层原位沉积以钝化表面。 具有低功函数的金属层沉积在电介质界面层的上方。 堆叠在大约500℃下在形成气体中退火以形成到SiC衬底的低电阻率欧姆接触。 将SiC衬底清洁并提供给处理室。 施加原位等离子体表面处理以进一步清洁基底的表面。 氧化硅介电界面层原位沉积以钝化表面。 施加可选的等离子体表面处理以进一步提高氧化硅介电界面层的性能。 在氧化硅介电界面层上沉积氧化铝栅极电介质层。

    METHOD FOR DEPOSITING A GATE OXIDE AND A GATE ELECTRODE SELECTIVELY
    94.
    发明申请
    METHOD FOR DEPOSITING A GATE OXIDE AND A GATE ELECTRODE SELECTIVELY 审中-公开
    选择选择氧化铝和门电极的方法

    公开(公告)号：US20130078793A1

    公开(公告)日：2013-03-28

    申请号：US13528446

    申请日：2012-06-20

    Applicant: Qingqing Sun ,  Ye Li ,  Runchen Fang ,  Pengfel Wang ,  Wei Zhang

    Inventor： Qingqing Sun ,  Ye Li ,  Runchen Fang ,  Pengfel Wang ,  Wei Zhang

    IPC: H01L21/28

    CPC classification number: H01L21/02178 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02307 ,  H01L21/28194 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66583

    Abstract: The present invention belongs to the technical field of integrated semiconductor circuits, and relates to a method for depositing a gate oxide and a gate electrode selectively. The present invention makes use of Octadecyltriethoxysilane's (ODTS') easy attachment to the Si—OH interface and difficult attachment to the Si—H interface, and selectively deposits the gate oxide and gate electrode materials, which avoids the unnecessary waste of materials and saves cost. Meanwhile, the present invention will transfer the etching of the gate oxide and gate electrode into the etching of SiO2 so as to reduce the difficulty of the etching process and increase the production efficiency.

    Abstract translation: 本发明属于集成半导体电路的技术领域，并且涉及选择性地沉积栅极氧化物和栅电极的方法。 本发明利用十八烷基三乙氧基硅烷（ODTS'）易于连接Si-OH界面并难以附着于Si-H界面，并选择性地沉积栅极氧化物和栅电极材料，从而避免不必要的材料浪费并节约成本 。 同时，本发明将栅极氧化物和栅电极的蚀刻转移到SiO 2的蚀刻中，以减少蚀刻工艺的难度并提高生产效率。

    Methods of forming silicon oxides and methods of forming interlevel dielectrics
    96.
    发明授权
    Methods of forming silicon oxides and methods of forming interlevel dielectrics 有权
    形成硅氧化物的方法和形成层间电介质的方法

    公开(公告)号：US08105956B2

    公开(公告)日：2012-01-31

    申请号：US12582181

    申请日：2009-10-20

    Applicant: Yunjun Ho ,  Brent Gilgen

    Inventor： Yunjun Ho ,  Brent Gilgen

    IPC: H01L21/31

    CPC classification number: H01L21/02164 ,  H01L21/02222 ,  H01L21/02307 ,  H01L21/02326 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76837 ,  H01L21/76897

    Abstract: A method of forming silicon oxide includes depositing a silicon nitride-comprising material over a substrate. The silicon nitride-comprising material has an elevationally outermost silicon nitride-comprising surface. Such surface is treated with a fluid that is at least 99.5% H2O by volume. A polysilazane-comprising spin-on dielectric material is formed onto the H2O-treated silicon nitride-comprising surface. The polysilazane-comprising spin-on dielectric material is oxidized to form silicon oxide. Other implementations are contemplated.

    Abstract translation: 形成氧化硅的方法包括在衬底上沉积含氮化硅的材料。 包含氮化硅的材料具有最高的最外面的含氮化硅的表面。 这种表面用体积至少为99.5％H 2 O的流体处理。 包含聚硅氮烷的旋涂电介质材料形成在经H2O处理的含氮化硅的表面上。 包含聚硅氮烷的旋涂电介质材料被氧化形成氧化硅。 考虑其他实现。

    Methods of Forming Silicon Oxides and Methods of Forming Interlevel Dielectrics
    98.
    发明申请
    Methods of Forming Silicon Oxides and Methods of Forming Interlevel Dielectrics 有权
    形成氧化硅的方法和形成介电层的方法

    公开(公告)号：US20110092061A1

    公开(公告)日：2011-04-21

    申请号：US12582181

    申请日：2009-10-20

    Applicant: Yunjun Ho ,  Brent Gilgen

    Inventor： Yunjun Ho ,  Brent Gilgen

    IPC: H01L21/3105 ,  H01L21/312 ,  H01L21/8234

    CPC classification number: H01L21/02164 ,  H01L21/02222 ,  H01L21/02307 ,  H01L21/02326 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76837 ,  H01L21/76897

    Abstract: A method of forming silicon oxide includes depositing a silicon nitride-comprising material over a substrate. The silicon nitride-comprising material has an elevationally outermost silicon nitride-comprising surface. Such surface is treated with a fluid that is at least 99.5% H2O by volume. A polysilazane-comprising spin-on dielectric material is formed onto the H2O-treated silicon nitride-comprising surface. The polysilazane-comprising spin-on dielectric material is oxidized to form silicon oxide. Other implementations are contemplated.

    Abstract translation: 形成氧化硅的方法包括在衬底上沉积含氮化硅的材料。 包含氮化硅的材料具有最高的最外面的含氮化硅的表面。 这种表面用体积至少为99.5％H 2 O的流体处理。 包含聚硅氮烷的旋涂电介质材料形成在经H2O处理的含氮化硅的表面上。 包含聚硅氮烷的旋涂电介质材料被氧化形成氧化硅。 考虑其他实现。

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