公开(公告)号：US20180080121A1

公开(公告)日：2018-03-22

申请号：US15795768

申请日：2017-10-27

Applicant: ASM IP Holding B.V.

Inventor： Delphine Longrie ,  Antti Juhani Niskanen ,  Han Wang ,  Qi Xie ,  Jan Willem Maes ,  Shang Chen ,  Toshiharu Watarai ,  Takahiro Onuma ,  Dai Ishikawa ,  Kunitoshi Namba

IPC: C23C16/02 ,  C23C16/455 ,  H01L21/768 ,  H01L21/285

CPC classification number: C23C16/02 ,  C23C16/06 ,  C23C16/345 ,  C23C16/4404 ,  C23C16/4405 ,  C23C16/45525 ,  C23C16/45536 ,  C23C16/56 ,  H01L21/28562 ,  H01L21/7685

Abstract: Metallic layers can be selectively deposited on one surface of a substrate relative to a second surface of the substrate. In some embodiments, the metallic layers are selectively deposited on a first metallic surface relative to a second surface comprising silicon. In some embodiments the reaction chamber in which the selective deposition occurs may optionally be passivated prior to carrying out the selective deposition process. In some embodiments selectivity of above about 50% or even about 90% is achieved.

公开(公告)号：US09916980B1

公开(公告)日：2018-03-13

申请号：US15380895

申请日：2016-12-15

Applicant: ASM IP Holding B.V.

Inventor： Werner Knaepen ,  Jan Willem Maes ,  Bert Jongbloed ,  Krzysztof Kamil Kachel ,  Dieter Pierreux ,  David Kurt De Roest

IPC: H01L21/033 ,  H01L21/027

CPC classification number: H01L21/0337 ,  C23C16/045 ,  C23C16/45525

Abstract: A method of forming a layer on a substrate is provided by providing the substrate with a hardmask material. The hardmask material is infiltrated with infiltration material during N infiltration cycles by: a) providing a first precursor to the hardmask material on the substrate in the reaction chamber for a first period T1; b) removing a portion of the first precursor for a second period T2; and, c) providing a second precursor to the hardmask material on the substrate for a third period T3, allowing the first and second precursor to react with each other forming the infiltration material.

公开(公告)号：US20180068846A1

公开(公告)日：2018-03-08

申请号：US15651203

申请日：2017-07-17

Applicant: ASM IP Holding B.V.

Inventor： Suvi P. Haukka ,  Fu Tang ,  Michael E. Givens ,  Jan Willem Maes ,  Qi Xie

IPC: H01L21/02 ,  H01L29/778 ,  H01L29/267 ,  H01L21/28 ,  H01L29/66 ,  H01L29/22 ,  H01L29/78

CPC classification number: H01L21/02175 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/02334 ,  H01L21/0237 ,  H01L21/02395 ,  H01L21/02557 ,  H01L21/02568 ,  H01L21/0262 ,  H01L21/02661 ,  H01L21/28264 ,  H01L29/2203 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/7786 ,  H01L29/78

Abstract: In some aspects, methods of forming a metal sulfide thin film are provided. According to some methods, a metal sulfide thin film is deposited on a substrate in a reaction space in a cyclical process where at least one cycle includes alternately and sequentially contacting the substrate with a first vapor-phase metal reactant and a second vapor-phase sulfur reactant. In some aspects, methods of forming a three-dimensional architecture on a substrate surface are provided. In some embodiments, the method includes forming a metal sulfide thin film on the substrate surface and forming a capping layer over the metal sulfide thin film. The substrate surface may comprise a high-mobility channel.

公开(公告)号：US09803277B1

公开(公告)日：2017-10-31

申请号：US15177195

申请日：2016-06-08

Applicant: ASM IP Holding B.V.

Inventor： Delphine Longrie ,  Antti Juhani Niskanen ,  Han Wang ,  Qi Xie ,  Jan Willem Maes ,  Shang Chen ,  Toshiharu Watarai ,  Takahiro Onuma ,  Dai Ishikawa ,  Kunitoshi Namba

IPC: C23C16/02 ,  H01L21/768 ,  H01L21/285 ,  C23C16/455

CPC classification number: C23C16/02 ,  C23C16/06 ,  C23C16/345 ,  C23C16/4404 ,  C23C16/4405 ,  C23C16/45525 ,  C23C16/45536 ,  C23C16/56 ,  H01L21/28562 ,  H01L21/7685

Abstract: Metallic layers can be selectively deposited on one surface of a substrate relative to a second surface of the substrate. In some embodiments, the metallic layers are selectively deposited on a first metallic surface relative to a second surface comprising silicon. In some embodiments the reaction chamber in which the selective deposition occurs may optionally be passivated prior to carrying out the selective deposition process. In some embodiments selectivity of above about 50% or even about 90% is achieved.

公开(公告)号：US09741815B2

公开(公告)日：2017-08-22

申请号：US14741246

申请日：2015-06-16

Applicant: ASM IP Holding B.V.

Inventor： Qi Xie ,  Fu Tang ,  Michael Eugene Givens ,  Jan Willem Maes

IPC: H01L29/51 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L29/517 ,  H01L21/28255 ,  H01L21/28264 ,  H01L29/513 ,  H01L29/66568

Abstract: In some aspects, methods of forming a metal selenide or metal telluride thin film are provided. According to some methods, a metal selenide or metal telluride thin film is deposited on a substrate in a reaction space in a cyclical deposition process where at least one cycle includes alternately and sequentially contacting the substrate with a first vapor-phase metal reactant and a second vapor-phase selenium or tellurium reactant. In some aspects, methods of forming three-dimensional architectures on a substrate surface are provided. In some embodiments, the method includes forming a metal selenide or metal telluride interface layer between a substrate and a dielectric. In some embodiments, the method includes forming a metal selenide or metal telluride dielectric layer between a substrate and a conductive layer.

公开(公告)号：US20150170907A1

公开(公告)日：2015-06-18

申请号：US14133509

申请日：2013-12-18

Applicant: ASM IP HOLDING B.V.

Inventor： Suvi P. Haukka ,  Fu Tang ,  Michael Givens ,  Jan Willem Maes ,  Qi Xie

IPC: H01L21/02

CPC classification number: H01L21/02175 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/02334 ,  H01L21/0237 ,  H01L21/02395 ,  H01L21/02557 ,  H01L21/02568 ,  H01L21/0262 ,  H01L21/02661 ,  H01L21/28264 ,  H01L29/2203 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/7786 ,  H01L29/78

Abstract: In some aspects, methods of forming a metal sulfide thin film are provided. According to some methods, a metal sulfide thin film is deposited on a substrate in a reaction space in a cyclical process where at least one cycle includes alternately and sequentially contacting the substrate with a first vapor-phase metal reactant and a second vapor-phase sulfur reactant. In some aspects, methods of forming a three-dimensional architecture on a substrate surface are provided. In some embodiments, the method includes forming a metal sulfide thin film on the substrate surface and forming a capping layer over the metal sulfide thin film. The substrate surface may comprise a high-mobility channel.

公开(公告)号：US09012278B2

公开(公告)日：2015-04-21

申请号：US14045680

申请日：2013-10-03

Applicant: ASM IP Holding B.V.

Inventor： Qi Xie ,  Vladimir Machkaoutsan ,  Jan Willem Maes

IPC: H01L21/8238 ,  H01L21/02 ,  B82Y10/00 ,  H01L29/66 ,  H01L29/775 ,  H01L29/06 ,  B82Y40/00

CPC classification number: H01L29/1037 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/0254 ,  H01L21/288 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823885 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/7391 ,  H01L29/775 ,  H01L29/7827 ,  H01L51/057 ,  Y10S977/89 ,  Y10S977/938

Abstract: In some embodiments, a method for manufacturing forms a semiconductor device, such as a transistor. A dielectric stack is formed on a semiconductor substrate. The stack comprises a plurality of dielectric layers separated by one of a plurality of spacer layers. Each of the plurality of spacer layers is formed of a different material than immediately neighboring layers of the plurality of dielectric layers. A vertically-extending hole is formed through the plurality of dielectric layers and the plurality of spacer layers. The hole is filled by performing an epitaxial deposition, with the material filling the hole forming a wire. The wire is doped and three of the dielectric layers are sequentially removed and replaced with conductive material, thereby forming upper and lower contacts to the wire and a gate between the upper and lower contacts. The wire may function as a channel region for a transistor.

Abstract translation: 在一些实施例中，制造方法形成诸如晶体管的半导体器件。 在半导体衬底上形成电介质叠层。 堆叠包括由多个间隔层之一隔开的多个电介质层。 多个间隔层中的每一个由与多个电介质层的紧邻层不同的材料形成。 通过多个介电层和多个间隔层形成垂直延伸的孔。 通过进行外延沉积来填充孔，其中材料填充形成线的孔。 导线被掺杂，并且三个电介质层被顺序地移除并被导电材料代替，由此形成上部和下部接触线和上部和下部触点之间的栅极。 导线可以用作晶体管的沟道区。

公开(公告)号：US20140273510A1

公开(公告)日：2014-09-18

申请号：US13829856

申请日：2013-03-14

Applicant: ASM IP HOLDING B.V.

Inventor： Jerry Chen ,  Vladimir Machkaoutsan ,  Brennan Milligan ,  Jan Willem Maes ,  Suvi Haukka ,  Eric Shero ,  Tom E. Blomberg ,  Dong Li

IPC: H01L21/02

CPC classification number: H01L21/28088 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/02321 ,  H01L21/02337 ,  H01L21/28044 ,  H01L21/2807 ,  H01L21/28556 ,  H01L21/28568

Abstract: Methods of treating metal-containing thin films, such as films comprising titanium carbide, with a silane/borane agent are provided. In some embodiments a film comprising titanium carbide is deposited on a substrate by an atomic layer deposition (ALD) process. The process may include a plurality of deposition cycles involving alternating and sequential pulses of a first source chemical that comprises titanium and at least one halide ligand, a second source chemical comprising metal and carbon, wherein the metal and the carbon from the second source chemical are incorporated into the thin film, and a third source chemical, wherein the third source chemical is a silane or borane that at least partially reduces oxidized portions of the titanium carbide layer formed by the first and second source chemicals. In some embodiments treatment forms a capping layer on the metal carbide film.

Abstract translation: 提供了用含有碳化钛的薄膜与含硅烷/硼烷剂一起处理含金属薄膜的方法。 在一些实施方案中，包含碳化钛的膜通过原子层沉积（ALD）工艺沉积在衬底上。 该方法可以包括多个沉积循环，其涉及包含钛和至少一种卤化物配体的第一源化学品的交替和顺序脉冲，包含金属和碳的第二源化学物质，其中来自第二源化学物质的金属和碳 和第三源化学品，其中第三源化学品是硅烷或硼烷，其至少部分地减少由第一和第二源化学品形成的碳化钛层的氧化部分。 在一些实施方案中，处理在金属碳化物膜上形成覆盖层。

公开(公告)号：US12068156B2

公开(公告)日：2024-08-20

申请号：US18305875

申请日：2023-04-24

Applicant: ASM IP HOLDING B.V.

Inventor： Jan Willem Maes ,  David Kurt de Roest ,  Oreste Madia

IPC: H01L21/02 ,  H01L21/311

CPC classification number: H01L21/0228 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31116

Abstract: Methods for selectively depositing silicon oxycarbide (SiOC) thin films on a dielectric surface of a substrate relative to a metal surface without generating significant overhangs of SiOC on the metal surface are provided. The methods can include at least one plasma enhanced atomic layer deposition (PEALD) cycle including alternately and sequentially contacting the substrate with a silicon precursor, a first Ar and H2 plasma, a second Ar plasma and an etchant.

公开(公告)号：US11970766B2

公开(公告)日：2024-04-30

申请号：US18097559

申请日：2023-01-17

Applicant: ASM IP Holding B.V.

Inventor： Ivo Johannes Raaijmakers ,  Jan Willem Maes ,  Werner Knaepen ,  Krzysztof Kamil Kachel

IPC: C23C16/04 ,  C23C16/44 ,  C23C16/448 ,  C23C16/455 ,  C23C16/46 ,  C23C16/52 ,  G03F7/20 ,  H01L21/02 ,  H01L21/027 ,  H01L21/033

CPC classification number: C23C16/045 ,  C23C16/4408 ,  C23C16/4412 ,  C23C16/4485 ,  C23C16/45523 ,  C23C16/45527 ,  C23C16/45544 ,  C23C16/45561 ,  C23C16/46 ,  C23C16/52 ,  G03F7/2004 ,  H01L21/02205 ,  H01L21/0228 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0273

Abstract: Examples of the disclosure relate to a sequential infiltration synthesis apparatus comprising:



a reaction chamber constructed and arranged to accommodate at least one substrate;
a first precursor flow path to provide the first precursor to the reaction chamber when a first flow controller is activated;
a second precursor flow path to provide a second precursor to the reaction chamber when a second flow controller is activated;
a removal flow path to allow removal of gas from the reaction chamber;
a removal flow controller to create a gas flow in the reaction chamber to the removal flow path
when the removal flow controller is activated; and,
a sequence controller operably connected to the first, second and removal flow controllers and the sequence controller being programmed to enable infiltration of an infiltrateable material provided on the substrate in the reaction chamber. The apparatus may be provided with a heating system.