公开(公告)号：US20100110765A1

公开(公告)日：2010-05-06

申请号：US12497964

申请日：2009-07-06

申请人： Wei Tian ,  Nurul Amin ,  Insik Jin ,  Ming Sun ,  Venu Vaithyanathan ,  YoungPil Kim ,  Chulmin Jung

发明人： Wei Tian ,  Nurul Amin ,  Insik Jin ,  Ming Sun ,  Venu Vaithyanathan ,  YoungPil Kim ,  Chulmin Jung

IPC分类号： G11C11/14 ,  G11C11/00 ,  G11C11/40

CPC分类号： G11C13/003 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/15 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/56 ,  G11C2213/76

摘要： A non-volatile memory cell with a programmable unipolar switching element, and a method of programming the memory element are disclosed. In some embodiments, the memory cell comprises a programmable bipolar resistive sense memory element connected in series with a programmable unipolar resistive sense switching element. The memory element is programmed to a selected resistance state by application of a selected write current in a selected direction through the cell, wherein a first resistance level is programmed by passage of a write current in a first direction and wherein a second resistance level is programmed by passage of a write current in an opposing second direction. The switching element is programmed to a selected resistance level to facilitate access to the selected resistance state of the memory element.

摘要翻译： 公开了一种具有可编程单极开关元件的非易失性存储单元，以及编程存储器元件的方法。 在一些实施例中，存储单元包括与可编程单极性电阻感测开关元件串联连接的可编程双极性电阻读出存储元件。 通过在所选择的方向上通过单元施加选择的写入电流将存储元件编程为所选择的电阻状态，其中通过沿第一方向的写入电流来编程第一电阻电平，并且其中第二电阻电平被编程 通过在相反的第二方向上的写入电流。 开关元件被编程为所选择的电阻水平以便于访问存储元件的所选择的电阻状态。

公开(公告)号：US20100102308A1

公开(公告)日：2010-04-29

申请号：US12390711

申请日：2009-02-23

申请人： Ming Sun ,  Michael Xuefei Tang ,  Insik Jin ,  Venkatram Venkatasamy ,  Philip George Pitcher ,  Nurul Amin

发明人： Ming Sun ,  Michael Xuefei Tang ,  Insik Jin ,  Venkatram Venkatasamy ,  Philip George Pitcher ,  Nurul Amin

IPC分类号： H01L29/12 ,  H01L29/00 ,  H01L21/00

CPC分类号： H01L45/085 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/146

摘要： Programmable metallization memory cells include an electrochemically active electrode and an inert electrode and an ion conductor solid electrolyte material between the electrochemically active electrode and the inert electrode. An electrically insulating oxide layer separates the ion conductor solid electrolyte material from the electrochemically active electrode.

摘要翻译： 可编程金属化存储单元包括在电化学活性电极和惰性电极之间的电化学活性电极和惰性电极以及离子导体固体电解质材料。 电绝缘氧化物层将离子导体固体电解质材料与电化学活性电极分离。

公开(公告)号：US20090194880A1

公开(公告)日：2009-08-06

申请号：US12023921

申请日：2008-01-31

申请人： Tao Feng ,  Francois Hebert ,  Ming Sun ,  Yueh-Se Ho

发明人： Tao Feng ,  Francois Hebert ,  Ming Sun ,  Yueh-Se Ho

IPC分类号： H01L23/48 ,  H01L21/304

CPC分类号： H01L29/7827 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/81 ,  H01L29/0657 ,  H01L29/41741 ,  H01L29/4175 ,  H01L29/45 ,  H01L29/49 ,  H01L29/7802 ,  H01L2224/02371 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/06183 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00

摘要： Power wafer level chip scale package (CSP) and process of manufacture are enclosed. The power wafer level chip scale package includes all source, gate and drain electrodes located on one side of the device, which is convenient for mounting to a printed circuit board (PCB) with solder paste.

摘要翻译： 封装了功率晶圆级芯片级封装（CSP）和制造工艺。 功率晶片级芯片级封装包括位于器件一侧的所有源极，栅极和漏极，方便用焊膏安装到印刷电路板（PCB）。

公开(公告)号：US07511361B2

公开(公告)日：2009-03-31

申请号：US11150489

申请日：2005-06-10

申请人： Xiaotian Zhang ,  Kai Liu ,  Ming Sun

发明人： Xiaotian Zhang ,  Kai Liu ,  Ming Sun

IPC分类号： H01L23/495

CPC分类号： H01L23/49562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/4943 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A DFN semiconductor package is disclosed. The package includes a leadframe having a die bonding pad formed integrally with a drain lead, a source lead bonding area and a gate lead bonding area, the source lead bonding area and the gate lead bonding area being of increased area, a die coupled to the die bonding pad, a die source bonding area coupled to the source lead bonding area and a die gate bonding area coupled to the gate lead bonding area, and an encapsulant at least partially covering the die, drain lead, gate lead bonding area and source lead bonding area.

摘要翻译： 公开了一种DFN半导体封装。 封装包括引线框架，其具有与漏极引线，源极引线接合区域和栅极引线接合区域整体形成的管芯接合焊盘，源极引线接合区域和栅极引线接合区域具有增加的面积， 芯片接合焊盘，耦合到源引线接合区域的管芯源极接合区域和耦合到栅极引线接合区域的管芯栅极结合区域，以及至少部分地覆盖管芯，漏极引线，栅极引线接合区域和源极引线 粘合区域。

公开(公告)号：US07466014B2

公开(公告)日：2008-12-16

申请号：US11786045

申请日：2007-04-09

申请人： Ming Sun ,  Demei Gong

发明人： Ming Sun ,  Demei Gong

IPC分类号： H01L23/495

CPC分类号： H01L23/4951 ,  H01L23/3114 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05568 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/00 ,  H01L2224/83851 ,  H01L2224/05599

摘要： A flip chip mounted semiconductor device package having a dimpled leadframe is disclosed. The semiconductor device package includes a leadframe having a plurality of source dimples and a gate dimple, and a semiconductor die having a plurality of source contact areas and a gate contact area corresponding to the leadframe source dimples and gate dimple respectively, the semiconductor die being flipped onto the leadframe such that cured conductive epoxy provides electrical and mechanical contact between the plurality of source contact areas and the plurality of source dimples, and the gate contact area and the gate dimple.

摘要翻译： 公开了一种具有凹陷引线框的倒装芯片安装的半导体器件封装。 半导体器件封装包括具有多个源极凹坑和栅极凹坑的引线框架，以及分别具有多个源极接触区域和对应于引线框源极凹坑和栅极凹坑的栅极接触区域的半导体管芯，半导体管芯被翻转 引导框架上，使得固化的导电环氧树脂在多个源极接触区域和多个源极凹坑以及栅极接触区域和栅极凹坑之间提供电和机械接触。

公开(公告)号：US20080247693A1

公开(公告)日：2008-10-09

申请号：US11696601

申请日：2007-04-04

申请人： Jonathan R. Schroeder ,  Ming Sun

发明人： Jonathan R. Schroeder ,  Ming Sun

IPC分类号： F16C33/02

CPC分类号： F16C33/08 ,  F16C33/107 ,  F16C33/201 ,  F16C2300/02 ,  Y10T29/49636

摘要： An improved sliding bearing apparatus and method utilize a snap-in polymer bearing insert having one or more identically shaped locking lugs, each of which are configured for locking engagement with a corresponding depression in a bearing housing, to thereby lock the bearing insert in place against relative movement either radially or axially with respect to the bearing housing. In a free-standing state, the insert may have a variety of shapes including cylindrical, non-cylindrical, or be flat and planar. An insert for a closed bearing is configured such that it may be trimmed to form an insert for an open bearing.

摘要翻译： 改进的滑动轴承装置和方法利用具有一个或多个相同形状的锁定凸耳的卡入式聚合物支承插入件，每个锁定凸耳被构造成与轴承壳体中的相应凹部锁定接合，从而将轴承插入件锁定在适当的位置，以抵抗 相对于轴承座径向或轴向相对运动。 在独立状态下，插入件可以具有各种形状，包括圆柱形，非圆柱形或扁平和平面。 用于封闭轴承的插入件构造成使得其可以被修整以形成用于开放轴承的插入件。

公开(公告)号：US20080233679A1

公开(公告)日：2008-09-25

申请号：US12154537

申请日：2008-05-22

申请人： Leeshawn Luo ,  Kai Liu ,  Ming Sun ,  Xiao Tian Zhang

发明人： Leeshawn Luo ,  Kai Liu ,  Ming Sun ,  Xiao Tian Zhang

IPC分类号： H01L21/58

CPC分类号： H01L21/568 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/49524 ,  H01L24/40 ,  H01L24/73 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/73253 ,  H01L2224/73255 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/37099 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor package and method for making a semiconductor package are disclosed. The semiconductor package has a top surface and a mounting surface and includes a die, a conducting connecting material, a plating material and an insulating material. The die has a processed surface facing towards the mounting surface of the semiconductor package. Exposed metal connections are at the processed surface of the die. The conducting connecting material is disposed on the exposed metal connections. The plating material is in contact with the conducting connecting material. The insulating material is formed around the conducting connecting material, and the plating material extends to the exterior of the insulating material.

摘要翻译： 公开了半导体封装和制造半导体封装的方法。 半导体封装具有顶表面和安装表面，并且包括管芯，导电连接材料，电镀材料和绝缘材料。 模具具有朝向半导体封装的安装表面的处理表面。 暴露的金属连接处于模具的加工表面。 导电连接材料设置在暴露的金属连接上。 电镀材料与导电连接材料接触。 绝缘材料围绕导电连接材料形成，电镀材料延伸到绝缘材料的外部。

公开(公告)号：US20080211070A1

公开(公告)日：2008-09-04

申请号：US11894240

申请日：2008-03-31

申请人： Ming Sun ,  Kai Liu ,  Xiao Tian Zhang ,  Yueh Se Ho ,  Leeshawn Luo

发明人： Ming Sun ,  Kai Liu ,  Xiao Tian Zhang ,  Yueh Se Ho ,  Leeshawn Luo

IPC分类号： H01L23/495

CPC分类号： H01L29/7813 ,  H01L24/33 ,  H01L29/045 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7811 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

摘要： This invention discloses a power device package for containing, protecting and providing electrical contacts for a power transistor. The power device package includes a top and bottom lead frames for directly no-bump attaching to the power transistor. The power transistor is attached to the bottom lead frame as a flip-chip with a source contact and a gate contact directly no-bumping attaching to the bottom lead frame. The power transistor has a bottom drain contact attaching to the top lead frame. The top lead frame further includes an extension for providing a bottom drain electrode substantially on a same side with the bottom lead frame. In a preferred embodiment, the power device package further includes a joint layer between device metal of source, gate or drain and top or bottom lead frame, through applying ultrasonic energy. In another embodiment, a layer of conductive epoxy or adhesive, a solder paste, a carbon paste, or other types of attachment agents for direct no-bumping attaching the power transistor to one of the top and bottom lead frames.

摘要翻译： 本发明公开了一种功率器件封装，用于容纳，保护和提供功率晶体管的电触头。 功率器件封装包括用于直接不连接到功率晶体管的顶部和底部引线框架。 功率晶体管作为具有源极接触的倒装芯片附接到底部引线框架，并且栅极接触件直接地不连接到底部引线框架上。 功率晶体管具有附接到顶部引线框架的底部漏极接触。 顶部引线框架还包括用于提供与底部引线框架基本上在同一侧上的底部漏极电极的延伸部分。 在优选实施例中，功率器件封装还包括通过施加超声波能量的源极，栅极或漏极以及顶部或底部引线框架的器件金属之间的接合层。 在另一个实施方案中，导电环氧树脂或粘合剂层，焊膏，碳糊或其它类型的附着剂用于将功率晶体管附接到顶引线框架和底引线框架之一的直接无凸起。

公开(公告)号：US20070290336A1

公开(公告)日：2007-12-20

申请号：US11799467

申请日：2007-04-30

申请人： Ming Sun ,  Lei Shi ,  Kai Liu

发明人： Ming Sun ,  Lei Shi ,  Kai Liu

IPC分类号： H01L23/48

CPC分类号： H01L23/49524 ,  H01L23/49562 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40249 ,  H01L2224/4103 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01055 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/37099

摘要： A semiconductor package is disclosed. The package includes a leadframe having drain, source and gate leads, a semiconductor die coupled to the leadframe, the semiconductor die having a plurality of metalized source areas and a metalized gate area, a patterned source connection having a plurality of dimples formed thereon coupling the source lead to the semiconductor die metalized source areas, a patterned gate connection having a dimple formed thereon coupling the gate lead to the semiconductor die metalized gate area, a semiconductor die drain area coupled to the drain lead, and an encapsulant covering at least a portion of the semiconductor die and drain, source and gate leads.

摘要翻译： 公开了半导体封装。 该封装包括具有漏极，源极和栅极引线的引线框架，耦合到引线框架的半导体管芯，具有多个金属化源极区域和金属化栅极区域的半导体管芯，具有形成在其上的多个凹坑的图案化源极连接， 源极引导到半导体芯片金属化源极区域，具有形成在其上的凹坑的图案化栅极连接将栅极引线耦合到半导体管芯金属化栅极区域，耦合到漏极引线的半导体管芯漏极区域和覆盖至少一部分的密封剂 的半导体管芯和漏极，源极和栅极引线。

公开(公告)号：US20070285835A1

公开(公告)日：2007-12-13

申请号：US11451236

申请日：2006-06-12

申请人： Ming Sun ,  Ibro M. Tabakovic ,  Steve C. Riemer ,  Mark T. Kief ,  Venkateswara R. Inturi ,  John A. Hawkins

发明人： Ming Sun ,  Ibro M. Tabakovic ,  Steve C. Riemer ,  Mark T. Kief ,  Venkateswara R. Inturi ,  John A. Hawkins

IPC分类号： G11B5/147

CPC分类号： G11B5/3113 ,  G11B5/1278 ,  G11B5/187 ,  G11B5/3143

摘要： A magnetic writing pole writes perpendicularly to a magnetic medium. The writing pole includes a multilayer structure with alternately electroplated magnetic layers and electroplated non-magnetic layers. The writing pole has a down-track thickness near the magnetic medium of less than about 500 nm.

摘要翻译： 磁写字柱垂直写入磁介质。 书写杆包括具有交替电镀的磁性层和电镀非磁性层的多层结构。 写磁极在磁介质附近具有小于约500nm的下轨道厚度。