公开(公告)号：US12100761B2

公开(公告)日：2024-09-24

申请号：US17578259

申请日：2022-01-18

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Kimin Jun ,  Il-Seok Son ,  Donald W. Nelson

IPC: H01L29/78 ,  H01L23/00 ,  H01L23/14 ,  H01L23/31 ,  H01L23/498 ,  H01L29/417 ,  H01L23/15

CPC classification number: H01L29/78 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/49827 ,  H01L24/00 ,  H01L24/05 ,  H01L29/41791 ,  H01L23/145 ,  H01L23/15 ,  H01L2224/0237 ,  H01L2224/04105 ,  H01L2224/0603 ,  H01L2224/16227

Abstract: An apparatus including a circuit structure including a first side including a device layer including a plurality of devices and an opposite second side; an electrically conductive contact coupled to one of the plurality of devices on the first side; and an electrically conductive interconnect disposed on the second side of the structure and coupled to the conductive contact. A method including forming a transistor device including a channel between a source and a drain and a gate electrode on the channel defining a first side of the device; forming an electrically conductive contact to one of the source and the drain from the first side; and forming an interconnect on a second side of the device, wherein the interconnect is coupled to the contact.

公开(公告)号：US11935933B2

公开(公告)日：2024-03-19

申请号：US18131336

申请日：2023-04-05

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Rishabh Mehandru ,  Aaron D. Lilak ,  Kimin Jun

IPC: H01L27/12 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L21/225 ,  H01L21/265

CPC classification number: H01L29/41791 ,  H01L21/823431 ,  H01L27/1266 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/78 ,  H01L29/785 ,  H01L21/2254 ,  H01L21/26513 ,  H01L29/66545

Abstract: An apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. A method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to one of the source region and the drain region from a second side of the device.

公开(公告)号：US20240063178A1

公开(公告)日：2024-02-22

申请号：US17821001

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Jimin Yao ,  Adel A. Elsherbini ,  Xavier Francois Brun ,  Kimin Jun ,  Shawna M. Liff ,  Johanna M. Swan ,  Yi Shi ,  Tushar Talukdar ,  Feras Eid ,  Mohammad Enamul Kabir ,  Omkar G. Karhade ,  Bhaskar Jyoti Krishnatreya

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/3107 ,  H01L24/16 ,  H01L24/08 ,  H01L2225/06548 ,  H01L2224/16227 ,  H01L2224/08145 ,  H01L2224/13116 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13109 ,  H01L2224/13118 ,  H01L24/13 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05613 ,  H01L2224/05609 ,  H01L2224/05605 ,  H01L24/05

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die and a through-dielectric via (TDV) surrounded by a dielectric material in a first layer, where the TDV has a greater width at a first surface and a smaller width at an opposing second surface of the first layer; a second die, surrounded by the dielectric material, in a second layer on the first layer, where the first die is coupled to the second die by interconnects having a pitch of less than 10 microns, and the dielectric material around the second die has an interface seam extending from a second surface of the second layer towards an opposing first surface of the second layer with an angle of less than 90 degrees relative to the second surface; and a substrate on and coupled to the second layer.

公开(公告)号：US20240063143A1

公开(公告)日：2024-02-22

申请号：US17891690

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Lance C. Hibbeler ,  Omkar Karhade ,  Chytra Pawashe ,  Kimin Jun ,  Feras Eid ,  Shawna Liff ,  Mohammad Enamul Kabir ,  Bhaskar Jyoti Krishnatreya ,  Tushar Talukdar ,  Wenhao Li

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/562 ,  H01L25/0657 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06548 ,  H01L2225/06582 ,  H01L2924/3511

Abstract: Techniques and mechanisms to mitigate warping of a composite chiplet. In an embodiment, multiple via structures each extend through an insulator material in one of multiple levels of a composite chiplet. The insulator material extends around an integrated circuit (IC) component in the level. For a given one of the multiple via structures, a respective annular structure extends around the via structure to mitigate a compressive (or tensile) stress due to expansion (or contraction) of the via structure. In another embodiment, the composite chiplet additionally or alternatively comprises a structural support layer on the multiple levels, wherein the structural support layer has formed therein or thereon dummy via structures or a warpage compensation film.

公开(公告)号：US11784165B2

公开(公告)日：2023-10-10

申请号：US17538200

申请日：2021-11-30

Applicant: INTEL CORPORATION

Inventor： Anup Pancholi ,  Kimin Jun

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/565 ,  H01L21/6835 ,  H01L24/73 ,  H01L24/92 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/73209 ,  H01L2224/92133 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06586

Abstract: An apparatus is provided which comprises: a first die having a first surface and a second surface, the first die comprising: a first layer formed on the first surface of the first die, and a second layer formed on the second surface of the first die; a second die coupled to the first layer; and a plurality of structures to couple the apparatus to an external component, wherein the plurality of structures is coupled to the second layer.

公开(公告)号：US11721649B2

公开(公告)日：2023-08-08

申请号：US17748877

申请日：2022-05-19

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Patrick Morrow ,  Henning Braunisch ,  Kimin Jun ,  Brennen Mueller ,  Shawna M. Liff ,  Johanna M. Swan ,  Paul B. Fischer

IPC: H01L23/66 ,  H01L23/64 ,  H01L23/36 ,  H01L23/49 ,  H01L23/538 ,  H01L23/34 ,  H01L49/02

CPC classification number: H01L23/645 ,  H01L23/34 ,  H01L23/66 ,  H01L28/10 ,  H01L2223/6677

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a die having a front side and a back side, the die comprising a first material and conductive contacts at the front side; and a thermal layer attached to the back side of the die, the thermal layer comprising a second material and a conductive pathway, wherein the conductive pathway extends from a front side of the thermal layer to a back side of the thermal layer.

公开(公告)号：US11569238B2

公开(公告)日：2023-01-31

申请号：US16222940

申请日：2018-12-17

Applicant: Intel Corporation

Inventor： Aaron Lilak ,  Willy Rachmady ,  Gilbert Dewey ,  Kimin Jun ,  Hui Jae Yoo ,  Patrick Morrow ,  Sean T. Ma ,  Ahn Phan ,  Abhishek Sharma ,  Cheng-Ying Huang ,  Ehren Mannebach

IPC: H01L29/66 ,  H01L21/336 ,  H01L27/108 ,  H01L49/02 ,  H01L29/423 ,  H01L23/528 ,  H01L29/786 ,  H01L29/06 ,  H01L29/49 ,  H01L29/10 ,  H01L29/417 ,  H01L29/51

Abstract: Embodiments herein describe techniques for a semiconductor device including a memory cell vertically above a substrate. The memory cell includes a metal-insulator-metal (MIM) capacitor at a lower device portion, and a transistor at an upper device portion above the lower device portion. The MIM capacitor includes a first plate, and a second plate separated from the first plate by a capacitor dielectric layer. The first plate includes a first group of metal contacts coupled to a metal electrode vertically above the substrate. The first group of metal contacts are within one or more metal layers above the substrate in a horizontal direction in parallel to a surface of the substrate. Furthermore, the metal electrode of the first plate of the MIM capacitor is also a source electrode of the transistor. Other embodiments may be described and/or claimed.

公开(公告)号：US11552104B2

公开(公告)日：2023-01-10

申请号：US16279693

申请日：2019-02-19

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Gilbert W. Dewey ,  Willy Rachmady ,  Rishabh Mehandru ,  Ehren Mannebach ,  Cheng-Ying Huang ,  Anh Phan ,  Patrick Morrow ,  Kimin Jun

IPC: H01L27/12 ,  H01L21/84

Abstract: Disclosed herein are stacked transistors with dielectric between channel materials, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, wherein a dielectric material is between channel materials of adjacent strata, and the dielectric material is surrounded by a gate dielectric.

公开(公告)号：US20220415837A1

公开(公告)日：2022-12-29

申请号：US17359380

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Feras Eid ,  Adel Elsherbini ,  Aleksandar Aleksov ,  Shawna Liff ,  Johanna Swan ,  Julien Sebot

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L21/56 ,  H01L25/00

Abstract: Techniques and mechanisms for mitigating stress on hybrid bonded interfaces in a multi-tier arrangement of integrated circuit (IC) dies. In an embodiment, first dies are bonded at a host die each via a respective one of first hybrid bond interfaces, wherein a second one or more dies are coupled to the host die each via a respective one of the first dies, and via a respective second hybrid bond interface. Stress at one of the hybrid bond interfaces is mitigated by properties of a first dielectric layer that extends to that hybrid bond interface. In another embodiment, stress at a given one of the hybrid bond interfaces is mitigated by properties of a dummy chip—or alternatively, properties of a patterned encapsulation structure—which is formed on the given hybrid bond interface.

公开(公告)号：US20220415555A1

公开(公告)日：2022-12-29

申请号：US17359165

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Qiang Yu ,  Adel Elsherbini ,  Kimin Jun

IPC: H01F27/06 ,  H01L23/64 ,  H01L23/522 ,  H01L23/528 ,  H01L49/02 ,  H01F27/28 ,  H01L21/50

Abstract: Methods and apparatus for inductor and transformer semiconductor devices using hybrid bonding technology are disclosed. An example semiconductor device includes a first standoff substrate; a second standoff substrate adjacent the first standoff substrate; and a conductive layer adjacent at least one of the first standoff substrate or the second standoff substrate.