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    Integrated circuit capable of operating in multiple orientations
    102.
    发明授权
    Integrated circuit capable of operating in multiple orientations 有权
    集成电路能够在多个方向上运行

    公开(公告)号：US06667561B2

    公开(公告)日：2003-12-23

    申请号：US10063036

    申请日：2002-03-13

    Applicant: David Stuart Baker

    Inventor： David Stuart Baker

    IPC: H01L2348

    CPC classification number: H05K3/303 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/0268 ,  H05K1/029 ,  H05K1/0295 ,  H05K3/306 ,  H05K2201/09954 ,  H05K2201/10704 ,  H05K2201/10734 ,  H05K2203/163 ,  Y02P70/613 ,  Y10T29/49139 ,  Y10T29/49169 ,  Y10T29/49208 ,  H01L2924/00

    Abstract: An integrated circuit design is provided capable of operating in multiple insertion orientations. In particular, the inventive circuit design includes an integrated circuit package having a plurality of contact elements extending from the integrated circuit package and arranged symmetrically thereon for enabling the integrated circuit to be inserted on a circuit board in at least two discrete orientations. A plurality of the contact elements are designated as orientation pins, the orientation pins being arranged such that, upon integrated circuit package power up, the orientation pins transmit orientation signals indicative of the integrated circuit packages insertion orientation in the circuit board. A plurality of multiplexer devices are provided for routing signals between the contact elements and integrated circuit functional circuitry in response to the orientation signals from the orientation pins.

    Abstract translation: 提供能够以多个插入方向操作的集成电路设计。 具体地，本发明的电路设计包括集成电路封装，其具有从集成电路封装延伸并且对称地布置的多个接触元件，以使集成电路能够以至少两个离散取向插入电路板上。 多个接触元件被指定为定位销，所述定向销布置成使得在集成电路封装上电时，定向销将指示集成电路封装在电路板中的插入取向的取向信号传送。 提供多个多路复用器装置用于响应于来自定向销的取向信号在接触元件和集成电路功能电路之间路由信号。

    Layout structure and method for supporting two different package techniques of CPU
    105.
    发明申请
    Layout structure and method for supporting two different package techniques of CPU 有权
    支持CPU的两种不同封装技术的布局结构和方法

    公开(公告)号：US20030141585A1

    公开(公告)日：2003-07-31

    申请号：US10064426

    申请日：2002-07-12

    Inventor： Nai-Shung Chang ,  Tsai-Sheng Chen ,  Shu-Hui Chen

    IPC: H01L021/44

    CPC classification number: H05K1/0295 ,  H05K1/0298 ,  H05K1/18 ,  H05K2201/09345 ,  H05K2201/09954 ,  H05K2201/10522 ,  H05K2201/10704 ,  H05K2201/10734

    Abstract: A layout structure of a central processing unit (CPU) that supports two different package techniques, comprising a motherboard that comprises the layout structure and a layout method. The layout structure of the preferred embodiment according to the present invention from up to down sequentially places a top signal layer, a grounded layer, a power layer having a grounded potential, and a bottom solder layer in the area where the signals of the CPU are coupled to the signals of the control chip, so that the signals that are placed on the bottom solder layer can refer to a grounded potential area of the power layer. Therefore, part of signals of the CPU that are coupled to the control chip can be placed on the bottom solder layer. Since the preferred embodiment of the present invention provides more flexibility in the placement design, a layout structure that supports the Pentium IV CPUs of different package techniques can be designed on the motherboard of the 4 layers stack structure, and these two CPUs can be supported by the same control chip.

    Abstract translation: 支持两种不同包装技术的中央处理单元（CPU）的布局结构，包括包括布局结构和布局方法的主板。 根据本发明的优选实施例的布局结构从上到下顺序地在CPU的信号区域中放置顶层信号层，接地层，具有接地电位的功率层和底部焊料层 耦合到控制芯片的信号，使得放置在底部焊料层上的信号可以指功率层的接地电位区域。 因此，耦合到控制芯片的CPU的部分信号可以放置在底部焊料层上。 由于本发明的优选实施例在布局设计中提供了更多的灵活性，因此可以在四层堆栈结构的主板上设计支持不同封装技术的Pentium IV CPU的布局结构，并且这两个CPU可以由 相同的控制芯片。

    Micro soldered connection
    107.
    发明申请
    Micro soldered connection 有权

    公开(公告)号：US20030102357A1

    公开(公告)日：2003-06-05

    申请号：US10261727

    申请日：2002-10-01

    Applicant: EMC Corporation

    Inventor： Stuart D. Downes

    IPC: B23K031/00

    CPC classification number: H01R12/585 ,  H01R43/0256 ,  H05K3/3447 ,  H05K3/3452 ,  H05K13/04 ,  H05K2201/10704 ,  H05K2201/10818 ,  H05K2201/10856 ,  H05K2201/10984 ,  H05K2203/0415 ,  H05K2203/0557

    Abstract: The invention is directed to techniques for forming a soldered connection using a pin having a channel. The channel enables the pin to form a secure connection with a via (e.g., by facilitating gas percolation out of the via hole during soldering to improve solder flow, by holding solder prior to pin insertion and soldering, or by facilitating accurate pin bending to hold solder or a pin insert prior to pin insertion and soldering) to improve connection system reliability and increase manufacturing yields. In one arrangement, the pin has a surface which includes (i) a first surface area, (ii) a second surface area that is substantially parallel to the first surface area, and (iii) a channel surface area which defines a channel that extends from the first surface area toward the second surface area. To form a soldered connection, the pin is inserted into a cavity defined by a via of a connecting member (e.g., a circuit board), in a direction that is parallel to a central axis of the via. The pin is then soldered to the via to establish an electrical pathway between the pin and the via. Depending on the particular arrangement, the channel generally facilitates the introduction of solder into the cavity of the via. Accordingly, the cavity dimension of the via can be smaller than that required for vias of a conventional reflow soldering approach (i.e., less than 100% of the maximum pin cross-section as for a conventional reflow soldering approach). Hence, the invention is suitable for use in high-density, micro-soldered connection arrangements (e.g., in situations with vias closer together than in the conventional reflow soldering approach).

    Pin grid array integrated circuit connecting device
    108.
    发明申请
    Pin grid array integrated circuit connecting device 有权
    针阵列集成电路连接装置

    公开(公告)号：US20030096514A1

    公开(公告)日：2003-05-22

    申请号：US10151679

    申请日：2002-05-20

    Inventor： Kwun-Yao Ho ,  Kung Moriss ,  Lin-Chou Tung

    IPC: H05K001/00

    CPC classification number: H05K1/141 ,  H05K3/3436 ,  H05K3/3447 ,  H05K2201/049 ,  H05K2201/10333 ,  H05K2201/10704 ,  H05K2201/2018 ,  H05K2201/2027

    Abstract: A pin grid array integrated circuit connecting device which comprises a substrate, a sliding slice, a guiding frame and a driving apparatus. Said substrate further comprises multiple holes to hold pins of a integrated circuit package, multiple conductive positioning components in the holes to hold said pins and connect said pins electrically, circuit device with proper circuit layout and multiple electrical connecting spots on the bottom of said substrate which connecting said multiple conductive positioning components thru said circuit device. The extra electronic components placed on said substrate will provide the additional function. Said sliding slice is placed on the top of said substrate and can be moved relatively. Multiple holes are placed on said sliding slice and positioned correspondingly to the holes on said substrate. Said guiding frame is placed on at least the two opposite sides of said substrate which guide said sliding move linearly along the extension of said guiding frame. Said driving apparatus is connecting to said sliding slice and, by rotating horizontally, drive said sliding slice to move in a proper manner linearly.

    Abstract translation: 一种针阵列集成电路连接装置，包括基板，滑动切片，引导框架和驱动装置。 所述衬底还包括多个孔以保持集成电路封装的引脚，孔中的多个导电定位部件以保持所述引脚并将所述引脚电连接，电路器件具有适当的电路布局和在所述衬底的底部上的多个电连接点 通过所述电路装置连接所述多个导电定位部件。 放置在所述基板上的额外的电子部件将提供额外的功能。 所述滑动片放置在所述衬底的顶部上并且可相对移动。 多个孔被放置在所述滑动切片上并相对于所述基底上的孔定位。 所述引导框架被放置在所述基板的至少两个相对的侧面上，所述两个相对侧沿着所述导向框架的延伸部线性地引导所述滑动移动。 所述驱动装置连接到所述滑动片，并且通过水平旋转驱动所述滑动片以适当的方式线性移动。

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