公开(公告)号：US09397188B2

公开(公告)日：2016-07-19

申请号：US14936609

申请日：2015-11-09

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/06 ,  H01L27/088 ,  H01L29/775 ,  H01L29/778 ,  H01L29/786 ,  H01L29/78 ,  B82Y10/00 ,  H01L21/02

CPC classification number: H01L29/158 ,  B82Y10/00 ,  H01L21/02603 ,  H01L23/66 ,  H01L27/0605 ,  H01L27/0886 ,  H01L29/045 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78696 ,  H01L2223/6677 ,  Y10S977/938

Abstract: A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.

Abstract translation: III-N族纳米线设置在基板上。 纳米线的纵向长度被限定为第一组III-N材料的沟道区域，与沟道区域的第一端电耦合的源极区域和与沟道区域的第二端电耦合的漏极区域。 第一组III-N材料上的第二组III-N材料用作纳米线表面上的电荷诱导层和/或阻挡层。 栅极绝缘体和/或栅极导体在通道区域内的纳米线周围同轴地包裹。 排水和源极接触件可以类似地同轴地围绕漏极和源极区域包裹。

公开(公告)号：US09391181B2

公开(公告)日：2016-07-12

申请号：US13723563

申请日：2012-12-21

Applicant: Intel Corporation

Inventor： Benjamin Chu-Kung ,  Van H. Le ,  Robert S. Chau ,  Sansaptak Dasgupta ,  Gilbert Dewey ,  Niti Goel ,  Jack T. Kavalieros ,  Matthew V. Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Willy Rachmady ,  Marko Radosavljevic ,  Han Wui Then ,  Nancy M. Zelick

IPC: H01L29/06 ,  H01L29/739 ,  H01L29/66 ,  H01L29/732 ,  H01L29/735 ,  H01L29/737 ,  H01L29/78 ,  H01L29/74

CPC classification number: H01L29/7391 ,  H01L29/0676 ,  H01L29/66242 ,  H01L29/6625 ,  H01L29/66356 ,  H01L29/66393 ,  H01L29/732 ,  H01L29/735 ,  H01L29/737 ,  H01L29/7371 ,  H01L29/7436 ,  H01L29/785

Abstract: An embodiment concerns forming an EPI film on a substrate where the EPI film has a different lattice constant from the substrate. The EPI film and substrate may include different materials to collectively form a hetero-epitaxial device having, for example, a Si and/or SiGe substrate and a III-V or IV film. The EPI film may be one of multiple EPI layers or films and the films may include different materials from one another and may directly contact one another. Further, the multiple EPI layers may be doped differently from another in terms of doping concentration and/or doping polarity. One embodiment includes creating a horizontally oriented hetero-epitaxial structure. Another embodiment includes a vertically oriented hetero-epitaxial structure. The hetero-epitaxial structures may include, for example, a bipolar junction transistor, heterojunction bipolar transistor, thyristor, and tunneling field effect transistor among others. Other embodiments are described herein.

Abstract translation: 一个实施例涉及在衬底上形成EPI膜，其中EPI膜具有与衬底不同的晶格常数。 EPI膜和衬底可以包括不同的材料以共同形成具有例如Si和/或SiGe衬底和III-V或IV膜的异质外延装置。 EPI膜可以是多个EPI层或膜中的一个，并且膜可以包括彼此不同的材料并且可以直接彼此接触。 此外，在掺杂浓度和/或掺杂极性方面，多个EPI层可以与另一个不同地被掺杂。 一个实施例包括产生水平取向的异质外延结构。 另一实施例包括垂直取向的异质外延结构。 异质外延结构可以包括例如双极结型晶体管，异质结双极晶体管，晶闸管和隧道场效应晶体管等。 本文描述了其它实施例。

公开(公告)号：US09373693B2

公开(公告)日：2016-06-21

申请号：US14535240

申请日：2014-11-06

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Sanaz K. Gardner ,  Robert S. Chau

IPC: H01L21/18 ,  H01L21/336 ,  H01L29/66 ,  H01L29/772 ,  H01L21/02 ,  H01L29/20 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/78696 ,  H01L21/02387 ,  H01L21/02389 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0251 ,  H01L21/02538 ,  H01L21/0254 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66409 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/772 ,  H01L29/785 ,  H01L29/78681

Abstract: A III-N semiconductor channel is compositionally graded between a transition layer and a III-N polarization layer. In embodiments, a gate stack is deposited over sidewalls of a fin including the graded III-N semiconductor channel allowing for formation of a transport channel in the III-N semiconductor channel adjacent to at least both sidewall surfaces in response to a gate bias voltage. In embodiments, a gate stack is deposited completely around a nanowire including a III-N semiconductor channel compositionally graded to enable formation of a transport channel in the III-N semiconductor channel adjacent to both the polarization layer and the transition layer in response to a gate bias voltage.

Abstract translation: III-N半导体通道在过渡层和III-N偏振层之间组成分级。 在实施例中，栅堆叠沉积在包括渐变III-N半导体沟道的鳍的侧壁上，允许在响应于栅极偏置电压的至少两个侧壁表面相邻的III-N半导体沟道中形成传输沟道。 在实施例中，栅极叠层完全沉积在包括III-N半导体沟道的纳米线周围，该纳米线被组成分级，以使得能够响应于栅极形成与偏振层和过渡层两者相邻的III-N半导体沟道中的传输沟道 偏压。

公开(公告)号：US09362369B2

公开(公告)日：2016-06-07

申请号：US14937819

申请日：2015-11-10

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Sanaz Gardner ,  Seung Hoon Sung ,  Robert S. Chau

IPC: H01L21/02 ,  H01L29/772 ,  H01L29/66 ,  H01L29/20 ,  H01L29/423 ,  H01L29/78 ,  H01L21/283

CPC classification number: H01L29/2003 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/0228 ,  H01L21/0254 ,  H01L21/283 ,  H01L21/28575 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/201 ,  H01L29/42356 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/802

Abstract: A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin.

公开(公告)号：US20150270265A1

公开(公告)日：2015-09-24

申请号：US14733865

申请日：2015-06-08

Applicant: INTEL CORPORATION

Inventor： Niti Goel ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Robert S. Chau ,  Willy Rachmady ,  Matthew V. Metz ,  Van H. Le ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Seung Hoon Sung

IPC: H01L27/092 ,  H01L21/02 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/267 ,  H01L29/06

CPC classification number: H01L27/092 ,  H01L21/0245 ,  H01L21/02538 ,  H01L21/823807 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78696

Abstract: An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor.

Abstract translation: 一种装置，包括在具有与第一格子结构不同的第二格子结构的缓冲材料中具有匹配的晶格结构的阱材料的阱上具有第一晶格结构的沟道材料的装置。 一种包括在缓冲材料中形成沟槽的方法; 在沟槽中形成n型阱材料，n型阱材料具有与缓冲材料的晶格结构不同的晶格结构; 并形成n型晶体管。 一种包括计算机的系统，包括处理器，所述处理器包括互补的金属氧化物半导体电路，所述辅助金属氧化物半导体电路包括包括沟道材料的n型晶体管，所述沟道材料在布置在具有不同于 第一晶格结构，n型晶体管耦合到p型晶体管。

公开(公告)号：US09112028B2

公开(公告)日：2015-08-18

申请号：US14263708

申请日：2014-04-28

Applicant: Intel Corporation

Inventor： Niti Goel ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Robert S. Chau ,  Willy Rachmady ,  Matthew V. Metz ,  Van H. Le ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Seung Hoon Sung

IPC: H01L21/02 ,  H01L29/78 ,  H01L21/84 ,  H01L27/12 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/092 ,  H01L21/0245 ,  H01L21/02538 ,  H01L21/823807 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78696

Abstract: An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor.

Abstract translation: 一种装置，包括在具有与第一格子结构不同的第二格子结构的缓冲材料中具有匹配的晶格结构的阱材料的阱上具有第一晶格结构的沟道材料的装置。 一种包括在缓冲材料中形成沟槽的方法; 在沟槽中形成n型阱材料，n型阱材料具有与缓冲材料的晶格结构不同的晶格结构; 并形成n型晶体管。 一种包括计算机的系统，包括处理器，所述处理器包括互补金属氧化物半导体电路，所述互补金属氧化物半导体电路包括包括沟道材料的n型晶体管，所述沟道材料在布置在具有不同于第二晶格结构的缓冲材料的阱中的第一晶格结构 第一晶格结构，n型晶体管耦合到p型晶体管。

公开(公告)号：US08853067B2

公开(公告)日：2014-10-07

申请号：US13957965

申请日：2013-08-02

Applicant: Intel Corporation

Inventor： Benjamin Chu-Kung ,  Uday Shah ,  Ravi Pillarisetty ,  Been-Yin Jin ,  Marko Radosavljevic ,  Willy Rachmady

IPC: H01L21/3205 ,  H01L29/78 ,  H01L21/762 ,  H01L29/775 ,  H01L29/06 ,  H01L29/66 ,  B82Y99/00

CPC classification number: H01L29/06 ,  B82Y99/00 ,  H01L21/76205 ,  H01L21/76224 ,  H01L29/0657 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7854

Abstract: A method is provided. The method includes forming a plurality of nanowires on a top surface of a substrate and forming an oxide layer adjacent to a bottom surface of each of the plurality of nanowires, wherein the oxide layer is to isolate each of the plurality of nanowires from the substrate.

Abstract translation: 提供了一种方法。 该方法包括在衬底的顶表面上形成多个纳米线并形成与多个纳米线中的每一个的底表面相邻的氧化物层，其中氧化物层将多个纳米线与衬底隔离。

公开(公告)号：US12191395B2

公开(公告)日：2025-01-07

申请号：US18494384

申请日：2023-10-25

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Shriram Shivaraman ,  Benjamin Chu-Kung ,  Yih Wang ,  Tahir Ghani

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/311 ,  H01L29/04 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H10B12/00

Abstract: Disclosed herein are dual gate trench shaped thin film transistors and related methods and devices. Exemplary thin film transistor structures include a non-planar semiconductor material layer having a first portion extending laterally over a first gate dielectric layer, which is over a first gate electrode structure, and a second portion extending along a trench over the first gate dielectric layer, a second gate electrode structure at least partially within the trench, and a second gate dielectric layer between the second gate electrode structure and the first portion.

公开(公告)号：US11843054B2

公开(公告)日：2023-12-12

申请号：US16016381

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Van H. Le ,  Seung Hoon Sung ,  Benjamin Chu-Kung ,  Miriam Reshotko ,  Matthew Metz ,  Yih Wang ,  Gilbert Dewey ,  Jack Kavalieros ,  Tahir Ghani ,  Nazila Haratipour ,  Abhishek Sharma ,  Shriram Shivaraman

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/423 ,  H01L23/522 ,  H01L29/66 ,  H01L29/49 ,  H10B12/00

CPC classification number: H01L29/78642 ,  H01L23/5226 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/78603 ,  H01L29/78645 ,  H10B12/05 ,  H10B12/30

Abstract: Embodiments herein describe techniques for a semiconductor device including a transistor. The transistor includes a first metal contact as a source electrode, a second metal contact as a drain electrode, a channel area between the source electrode and the drain electrode, and a third metal contact aligned with the channel area as a gate electrode. The first metal contact may be located in a first metal layer along a first direction. The second metal contact may be located in a second metal layer along the first direction, in parallel with the first metal contact. The third metal contact may be located in a third metal layer along a second direction substantially orthogonal to the first direction. The third metal layer is between the first metal layer and the second metal layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20230223475A1

公开(公告)日：2023-07-13

申请号：US18174825

申请日：2023-02-27

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Ravi Pillarisetty ,  Brian S. Doyle ,  Elijah V. Karpov ,  Prashant Majhi ,  Gilbert W. Dewey ,  Benjamin Chu-Kung ,  Van H. Le ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/78391 ,  H01L29/6684

Abstract: Disclosed herein are transistors with ferroelectric gates, and related methods and devices. For example, in some embodiments, a transistor may include a channel material, and a gate stack, and the gate stack may include a gate electrode material and a ferroelectric material between the gate electrode material and the channel material.