公开(公告)号：US20150155319A1

公开(公告)日：2015-06-04

申请号：US14559006

申请日：2014-12-03

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Romain Girard Desprolet ,  Sandrine Lhostis ,  Salim Boutami ,  Michel Marty

IPC: H01L27/146

CPC classification number: H01L31/02162 ,  G02B5/203 ,  H01L27/14621 ,  H01L27/14629 ,  H01L27/1463 ,  H01L27/14685 ,  H01L27/14687 ,  H01L31/02165 ,  H01L31/02327

Abstract: An integrated imaging device supports front face illumination with one or more photosensitive regions formed in a substrate. A lower dielectric region is provided over the substrate, the lower dielectric region having an upper face. A metal optical filter having a metal pattern is provided on the upper face (or extending into the lower dielectric region from the upper face). An upper dielectric region is provided on top of the lower dielectric region and metal optical filter. The lower dielectric region is at least part of a pre-metal dielectric layer, and the upper dielectric region is at least part of a metallization layer.

Abstract translation: 集成成像装置支持在基板中形成的一个或多个感光区域的前面照明。 下部电介质区域设置在衬底上，下部电介质区域具有上表面。 具有金属图案的金属滤光器设置在上表面（或从上表面延伸到下介电区域中）。 在下部电介质区域和金属光学滤波器的顶部设置有上部电介质区域。 下电介质区域是预金属介电层的至少一部分，并且上电介质区域是金属化层的至少一部分。

公开(公告)号：US09006851B2

公开(公告)日：2015-04-14

申请号：US13198458

申请日：2011-08-04

Applicant: Christophe Regnier ,  Olivier Hinsinger ,  Daniel Gloria ,  Pascal Urard

Inventor： Christophe Regnier ,  Olivier Hinsinger ,  Daniel Gloria ,  Pascal Urard

IPC: H01L31/0203 ,  H01L25/16 ,  H01L31/0224 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L25/16 ,  H01L21/76838 ,  H01L23/481 ,  H01L25/0652 ,  H01L31/02245 ,  H01L2223/6677 ,  H01L2224/16145 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15192 ,  Y02E10/50 ,  H01L2224/81

Abstract: A stand-alone device comprising a silicon wafer having its front surface including a first layer of a first conductivity type and a second layer of a second conductivity type forming a photovoltaic cell; first vias crossing the wafer from the rear surface of the first layer and second vias crossing the wafer from the rear surface of the second layer; metallization levels on the rear surface of the wafer, the external level of these metallization levels defining contact pads; an antenna formed in one of the metallization levels; and one or several chips assembled on said pads; the metallization levels being shaped to provide selected interconnects between the different elements of the device.

Abstract translation: 一种独立装置，包括具有其前表面的硅晶片，该硅晶片包括形成光伏电池的第一导电类型的第一层和第二导电类型的第二层; 从第一层的后表面穿过晶片的第一通孔和从第二层的后表面穿过晶片的第二过孔; 在晶片的后表面上的金属化水平，这些金属化水平的外部水平限定接触垫; 形成在金属化层之一中的天线; 以及组装在所述垫上的一个或多个芯片; 金属化水平被成形为在装置的不同元件之间提供选定的互连。

公开(公告)号：US09000964B2

公开(公告)日：2015-04-07

申请号：US14294300

申请日：2014-06-03

Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

Inventor： Stéphane Le Tual ,  Pratap Narayan Singh

IPC: H03M1/00 ,  H03M1/08 ,  H03K3/013 ,  G11C27/02 ,  H03K19/0185

CPC classification number: H03M1/08 ,  G11C27/024 ,  G11C27/026 ,  H03K3/013 ,  H03K19/018528

Abstract: The invention concerns a circuit comprising: a first transistor (202) having a first main current node coupled to a first voltage signal (CNVDD), a control node coupled to a second voltage signal (CPVDD) and a second main current node coupled to an output node (206) of the circuit; a second transistor (204) having a first main current node coupled to a third voltage signal (CNGND), a control node coupled to a fourth voltage signal (CPGND) and a second main current node coupled to said output node of the circuit; and circuitry (210, 212) adapted to generate said first, second, third and fourth voltage signals based on a pair of differential input signals (CP, CN), wherein said first and second voltage signals are both referenced to a first supply voltage (VDD) and wherein said third and fourth voltage signals are both referenced to a second supply voltage (GND).

Abstract translation: 本发明涉及一种电路，包括：具有耦合到第一电压信号（CNVDD）的第一主电流节点的第一晶体管（202），耦合到第二电压信号（CPVDD）的控制节点和耦合到第一电流信号 输出节点（206）; 第二晶体管（204），其具有耦合到第三电压信号（CNGND）的第一主电流节点，耦合到第四电压信号（CPGND）的控制节点和耦合到所述电路的所述输出节点的第二主电流节点; 以及适于基于一对差分输入信号（CP，CN）产生所述第一，第二，第三和第四电压信号的电路（210,212），其中所述第一和第二电压信号都参考第一电源电压 VDD），并且其中所述第三和第四电压信号都参考第二电源电压（GND）。

公开(公告)号：US20150091089A1

公开(公告)日：2015-04-02

申请号：US14499545

申请日：2014-09-29

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Heimanu Niebojewski ,  Yves Morand ,  Cyrille Le Royer ,  Olivier Rozeau

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/515 ,  H01L29/0843 ,  H01L29/4983 ,  H01L29/4991 ,  H01L29/51 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/78

Abstract: A MOS transistor has a gate insulator layer that is made of a material of high dielectric constant deposited on a substrate. The gate insulator layer extends, with a constant thickness, under and beyond a gate stack. Spacers of low dielectric constant are formed on either side of the gate stack and vertically separated from the substrate by the extension of the gate insulator layer beyond the sides of the gate stack. The spacers of low dielectric constant are preferably air spacers.

Abstract translation: MOS晶体管具有由沉积在衬底上的高介电常数材料制成的栅极绝缘体层。 栅极绝缘体层以恒定的厚度延伸到栅极堆叠之下和之外。 通过栅极绝缘体层的延伸超过栅极叠层的侧面，在栅极叠层的任一侧上形成具有低介电常数的隔板并与衬底垂直分离。 低介电常数的间隔物优选为空气间隔物。

公开(公告)号：US08996874B2

公开(公告)日：2015-03-31

申请号：US10817325

申请日：2004-04-01

Applicant: Stéphan Courcambeck ,  Claude Anguille

Inventor： Stéphan Courcambeck ,  Claude Anguille

IPC: H04L9/00 ,  G06F12/14 ,  G06F21/53 ,  G06F21/62

CPC classification number: G06F12/1475 ,  G06F21/53 ,  G06F21/6218

Abstract: A method for authorizing an access to a table of address correspondence between a multitask CPU and at least one memory containing several programs, consisting of calculating, on each task change of the CPU, a signature of at least part of the program instruction lines, and checking the conformity of this signature with a signature recorded upon previous execution of the involved program.

Abstract translation: 一种用于授权访问多任务CPU和至少一个包含若干程序的存储器之间的地址对应表的方法，包括在CPU的每个任务改变上计算至少部分程序指令行的签名，以及 检查此签名的一致性与之前执行相关程序时记录的签名。

公开(公告)号：US08981529B2

公开(公告)日：2015-03-17

申请号：US13745613

申请日：2013-01-18

Applicant: STMicroelectronics S.A. ,  International Business Machines Corporation

Inventor： Yvan Morandini ,  Romain Debrouke

IPC: H01L29/93 ,  H01L29/66 ,  H03B1/00 ,  H03J3/20 ,  H03B5/12

CPC classification number: H01L29/93 ,  H01L29/66174 ,  H03B1/00 ,  H03B5/1212 ,  H03B5/1253 ,  H03J3/20 ,  H03J2200/10

Abstract: A variable capacitance device including: first and second transistors coupled in parallel between first and second nodes of the capacitive device, a control node of the first transistor being adapted to receive a control signal, and a control node of the second transistor being adapted to receive the inverse of the control signal, wherein the first and second transistors are formed in a same semiconductor well.

Abstract translation: 一种可变电容装置，包括：第一和第二晶体管并联耦合在电容性装置的第一和第二节点之间，第一晶体管的控制节点适于接收控制信号，第二晶体管的控制节点适于接收 控制信号的反相，其中第一和第二晶体管形成在相同的半导体阱中。

公开(公告)号：US08980702B2

公开(公告)日：2015-03-17

申请号：US14177614

申请日：2014-02-11

Applicant: Commissariat a l'Energie Atomique et aux ene Alt ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Heimanu Niebojewski ,  Yves Morand ,  Maud Vinet

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78603

Abstract: A method for manufacturing a transistor includes forming a stack of semiconductor on insulator type layers including at least one substrate, surmounted by a first insulating layer and an active layer to form a channel for the transistor; forming a gate stack on the active layer; producing a source and a drain including forming, on either side of the gate stack, cavities by at least one step of etching the active layer, the first insulating layer, and part of the substrate selectively to the gate stack to remove the active layer, the first insulating layer, and a portion of the substrate outside regions situated below the gate stack; forming a second insulating layer on the bared surfaces of the substrate, to form a continuous insulating layer with the first insulating layer; baring of the lateral ends of the channel; and the filling of the cavities by epitaxy.

Abstract translation: 一种制造晶体管的方法，包括：形成绝缘体上半导体层的叠层，其包括至少一个衬底，其被第一绝缘层和有源层所覆盖以形成晶体管的沟道; 在有源层上形成栅叠层; 产生源极和漏极，包括在栅叠层的任一侧通过至少一个步骤，至少一个步骤，将有源层，第一绝缘层和衬底的一部分选择性地栅极堆叠以形成去除有源层， 所述第一绝缘层和位于所述栅叠层下方的所述衬底外部区域的一部分; 在所述基板的裸露表面上形成第二绝缘层，以形成具有所述第一绝缘层的连续绝缘层; 通道的横向端部露出; 并通过外延填充空腔。

公开(公告)号：US20150028488A1

公开(公告)日：2015-01-29

申请号：US14339630

申请日：2014-07-24

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT ,  STMICROELECTRONICS SA

Inventor： Jean-Philippe COLONNA ,  Perceval COUDRAIN

IPC: H01L23/00 ,  H01L21/306 ,  H01L21/768

CPC classification number: H01L24/19 ,  H01L21/30604 ,  H01L21/4853 ,  H01L21/6836 ,  H01L21/7685 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/20 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/13009 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13084 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13181 ,  H01L2224/13186 ,  H01L2224/1356 ,  H01L2224/13565 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13666 ,  H01L2224/13671 ,  H01L2224/13681 ,  H01L2224/13686 ,  H01L2224/14181 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The invention relates to a method for producing an interconnection pad on a conducting element comprising an upper face and a side wall; the method being executed from a substrate at least the upper face of which is insulating; the conducting element going through at least an insulating portion of the substrate, the method being characterized in that it comprises the sequence of the following steps: a step of embossing the conducting element, a step of forming, above the upper insulating face of the substrate, a stack of layers comprising at least one electrically conducting layer and one electrically resistive layer, a step of partially removing the electrically resistive layer, a step of electrolytic growth on the portion of the electrically conducting layer so as to form at least one interconnection pad on said conducting element.

Abstract translation: 本发明涉及一种用于在导电元件上制造互连焊盘的方法，包括上表面和侧壁; 所述方法从至少其上表面绝缘的衬底执行; 所述导电元件至少穿过所述基板的绝缘部分，所述方法的特征在于，其包括以下步骤的顺序：对所述导电元件进行压花的步骤，在所述基板的上绝缘面上方形成步骤 ，包括至少一个导电层和一个电阻层的层叠层，部分去除所述电阻层的步骤，在所述导电层的所述部分上的电解生长步骤，以便形成至少一个互连衬垫 在所述导电元件上。

公开(公告)号：US08937334B2

公开(公告)日：2015-01-20

申请号：US13523520

申请日：2012-06-14

Applicant: Thomas Benoist ,  Philippe Galy ,  Johan Bourgeat ,  Frank Jezequel ,  Nicolas Guitard

Inventor： Thomas Benoist ,  Philippe Galy ,  Johan Bourgeat ,  Frank Jezequel ,  Nicolas Guitard

IPC: H01L29/747 ,  H01L27/02

CPC classification number: H01L29/747 ,  H01L27/0262

Abstract: A triggerable bidirectional semiconductor device has two terminals and at least one gate. The device comprises, within a layer of silicon on insulator, a central semiconductor zone incorporating the at least one gate and comprising a central region having a first conductivity type, two intermediate regions having a second conductivity type respectively arranged on either side of and in contact with the central region, two semiconductor end zones respectively arranged on either side of the central zone, each end zone comprising two end regions having opposite types of conductivity, in contact with the adjacent intermediate region, the two end regions of each end zone being mutually connected electrically in order to form the two terminals of the device.

Abstract translation: 可触发的双向半导体器件具有两个端子和至少一个栅极。 该器件在绝缘体上的硅层内包括结合有至少一个栅极并包括具有第一导电类型的中心区域的中心半导体区域，具有分别设置在接触的两侧和接触的第二导电类型的两个中间区域 中心区域分别设置在中心区域的两侧的两个半导体端部区域，每个端部区域包括具有与相邻中间区域相接触的相反导电类型的两个端部区域，每个端部区域的两个端部区域相互 电连接以形成装置的两个端子。

公开(公告)号：US08923408B2

公开(公告)日：2014-12-30

申请号：US10702220

申请日：2003-11-05

Applicant: Denis Dutey ,  Nikola Cornij

Inventor： Denis Dutey ,  Nikola Cornij

IPC: H04N7/12 ,  H04N11/02 ,  H04N11/04 ,  H04N21/258 ,  H04N19/12 ,  H04N21/2662 ,  H04N19/172 ,  H04N19/156 ,  H04N19/46 ,  H04N19/112 ,  H04N5/45 ,  H04N7/01 ,  H04N9/82 ,  H04N19/40 ,  H04N5/44 ,  H04N5/85 ,  H04N9/804 ,  H04N21/488

CPC classification number: H04N21/2662 ,  H04N5/4401 ,  H04N5/45 ,  H04N5/85 ,  H04N7/012 ,  H04N9/8042 ,  H04N9/8227 ,  H04N19/112 ,  H04N19/12 ,  H04N19/156 ,  H04N19/172 ,  H04N19/40 ,  H04N19/46 ,  H04N21/25808 ,  H04N21/4312 ,  H04N21/4348 ,  H04N21/4355 ,  H04N21/4884

Abstract: A method of transcoding a sub-picture unit each comprising encoded sub-picture pixel data including sub-picture lines separated into at least a first field and a second field as well as a set of display control commands associated with the sub-picture pixel data, comprises the step of pre-processing (53) the display control commands to prepare transcoding to frame format. Encoded lines of said top and bottom fields are then merged (56,73) into a single encoded frame and the display control commands are modified (56,74) according to changes in encoded sub-picture pixel data before outputting.

Abstract translation: 一种副图像单元的代码转换方法，每个子图像单元包括被编码的子图像像素数据，该子图像像素数据包括分成至少第一场和第二场的子图像线以及与子图像像素数据相关联的一组显示控制命令 包括对显示控制命令进行预处理（53）以准备对帧格式的转码的步骤。 然后，所述顶部和底部场的编码行被合并（56,73）到单个编码帧中，并且根据编码的子图像像素数据在输出之前的变化来修改显示控制命令（56,74）。