公开(公告)号：US20090095518A1

公开(公告)日：2009-04-16

申请号：US12245025

申请日：2008-10-03

Applicant: Yoshitaka Matsushita ,  Kazuhiro Oshima ,  Akio Horiuchi

Inventor： Yoshitaka Matsushita ,  Kazuhiro Oshima ,  Akio Horiuchi

IPC: H05K1/11 ,  H05K3/00

CPC classification number: H05K3/284 ,  H01L21/481 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49861 ,  H01L24/16 ,  H01L2221/68345 ,  H01L2224/16 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/15312 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19106 ,  H01L2924/3511 ,  H05K2201/09136 ,  H05K2201/10318 ,  H05K2201/10977 ,  H05K2203/1316 ,  Y10T29/49124

Abstract: A wiring board has a wiring member, a first reinforcing member and a second reinforcing member. The wiring member has wiring layers and insulating layers which are stacked, and the wiring layers include a first connecting electrode formed on a surface of the wiring member and a second connecting electrode formed on a back surface of the wiring member. A pin is formed on the second connecting electrode. The second reinforcing member is formed by a resin and serves to reinforce the wiring member. The first reinforcing member is formed on the whole back surface of the wiring member except for the pin provided on the second connecting electrode.

Abstract translation: 布线板具有布线构件，第一加强构件和第二加强构件。 布线构件具有层叠的布线层和绝缘层，并且布线层包括形成在布线构件的表面上的第一连接电极和形成在布线构件的背面上的第二连接电极。 销形成在第二连接电极上。 第二加强构件由树脂形成，用于加强布线构件。 除了设置在第二连接电极上的销之外，第一加强构件形成在布线构件的整个背面上。

公开(公告)号：US07504718B2

公开(公告)日：2009-03-17

申请号：US11125499

申请日：2005-05-10

Applicant: Michael Anthony Gaynes ,  Kathleen Conlon Hinge ,  John Ulrich Knickerbocker

Inventor： Michael Anthony Gaynes ,  Kathleen Conlon Hinge ,  John Ulrich Knickerbocker

IPC: H01L23/02 ,  H01L29/40

CPC classification number: H05K1/0271 ,  H01L23/562 ,  H01L2224/16 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/15311 ,  H05K1/181 ,  H05K3/0058 ,  H05K2201/068 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2201/2009 ,  H01L2924/00 ,  H01L2224/0401

Abstract: Apparatus and methods are provided for constructing balanced semiconductor chip package structures that minimize bowing, in-plane strain and/or other thermally induced mechanical strains that may arise during thermal cycling, to thus prevent structural damage to chip package structures.

Abstract translation: 提供了用于构建平衡的半导体芯片封装结构的装置和方法，其使在热循环期间可能出现的弯曲，面内应变和/或其它热诱导的机械应变最小化，从而防止对芯片封装结构的结构损坏。

公开(公告)号：US20090050353A1

公开(公告)日：2009-02-26

申请号：US12178055

申请日：2008-07-23

Applicant: Nobuaki HASHIMOTO

Inventor： Nobuaki HASHIMOTO

IPC: H05K1/02

CPC classification number: H05K3/325 ,  G02F2001/13456 ,  H01L2224/05001 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/13008 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K3/305 ,  H05K2201/0314 ,  H05K2201/10128 ,  H05K2201/10674 ,  H05K2201/10977 ,  H01L2224/05099

Abstract: A mounting structure of an electronic component includes: a bump electrode included in the electronic component, the bump electrode having an internal resin as a core and a conductive film covering a surface of the internal resin, and elastically deforming so as to follow a shape of at least one corner of a terminal so that the conductive film makes direct conductive contact with at least part of a top surface of the terminal and at least part of a surface along a thickness direction of the terminal; a substrate having the terminal and the electronic component that is mounted on the substrate; and a holding unit provided to the substrate and the electronic component so as to hold a state in which the bump electrode electrically deformed makes conductive contact with the terminal.

Abstract translation: 电子部件的安装结构包括：包括在电子部件中的凸块电极，具有内部树脂作为芯的凸块电极和覆盖内部树脂的表面的导电膜，并且弹性变形，以便遵循 端子的至少一个角部，使得导电膜与端子的顶表面的至少一部分和沿着端子的厚度方向的表面的至少一部分直接导电接触; 具有安装在基板上的端子和电子部件的基板; 以及保持单元，其设置到所述基板和所述电子部件，以保持所述凸起电极变形的状态与所述端子导电接触。

公开(公告)号：US07487586B2

公开(公告)日：2009-02-10

申请号：US10737853

申请日：2003-12-18

Applicant: Akiko Matsumura ,  Yuji Hotta

Inventor： Akiko Matsumura ,  Yuji Hotta

IPC: H05K3/30

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01077 ,  H05K3/3452 ,  H05K3/3457 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2203/1189 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  H01L2224/0401

Abstract: A process for semiconductor device production by which the reliability of connection with bumps can be easily heightened with higher certainty. The process for producing a semiconductor device comprising a substrate having bumps formed thereon, comprises covering the bumps with an adhesive film which has a modulus of elasticity (−55° C.) of from 100 MPa to 5 GPa and has a thickness corresponding to from 5 to 40% of the height of the bumps, and then disposing the adhesive film on the substrate so that the bumps pierce through the adhesive film and come to protrude therefrom.

Abstract translation: 一种用于半导体器件生产的方法，通过该方法可以更高的确定性容易地提高与凸块的连接的可靠性。 包括其上形成有凸起的基板的半导体器件的制造方法包括：使用具有100MPa至5GPa的弹性模量（-55℃）的粘合剂膜覆盖凸块，并且具有对应于 凸起的高度的5〜40％，然后将粘合剂膜设置在基板上，使得突起穿过粘合膜并从其突出。

公开(公告)号：US20090014896A1

公开(公告)日：2009-01-15

申请号：US12216850

申请日：2008-07-11

Applicant: Shih-Ping Hsu

Inventor： Shih-Ping Hsu

IPC: H01L23/52

CPC classification number: H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01082 ,  H05K3/3436 ,  H05K2201/10234 ,  H05K2201/10977 ,  H05K2201/10992 ,  H05K2203/041 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2924/00

Abstract: A flip-chip package structure is disclosed, which comprises: a packaging substrate having an upper surface and a plurality of conductive pads formed on the upper surface; a semiconductor chip having an active surface and a plurality of electrode pads formed on the active surface; and a plurality of first solder bumps; wherein each first solder bump connects to an electrode pad and a conductive pad, and each first solder bump contains a solid grain.

Abstract translation: 公开了一种倒装芯片封装结构，其包括：具有上表面和形成在上表面上的多个导电焊盘的封装基板; 具有活性表面的半导体芯片和形成在所述有源表面上的多个电极焊盘; 和多个第一焊料凸块; 其中每个第一焊料凸块连接到电极焊盘和导电焊盘，并且每个第一焊料凸块包含固体颗粒。

公开(公告)号：US07476975B2

公开(公告)日：2009-01-13

申请号：US11176782

申请日：2005-07-07

Applicant: Yoshiharu Ogata

Inventor： Yoshiharu Ogata

IPC: H01L23/52

CPC classification number: H05K3/305 ,  H01L21/563 ,  H01L23/3128 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/29007 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K1/0271 ,  H05K3/3452 ,  H05K2201/09772 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2924/00014

Abstract: A semiconductor device comprises a wiring substrate including a wiring pattern; a semiconductor chip installed on the wiring substrate, including a plurality of pads formed on a surface of the semiconductor chip, which opposes the wiring substrate; a first resin layer covering over a part of the wiring pattern within a region of overlapping the semiconductor chip; and a second resin layer installed between the semiconductor chip and the first resin layer. The pads are oppose to and coupled with a part of the wiring pattern exposed over the first resin layer; and the linear expansion coefficient of the wiring substrate is larger than that of the semiconductor chip, the elastic modulus of the wiring substrate is lower than that of the semiconductor chip and the linear expansion coefficient of the first resin layer is larger than that of the second resin layer. The elastic modulus of the first resin layer is lower than that of the second resin layer.

Abstract translation: 半导体器件包括：布线基板，其包括布线图案; 安装在所述布线基板上的半导体芯片，包括与所述布线基板相对的形成在所述半导体芯片的表面上的多个焊盘; 覆盖所述布线图案的与所述半导体芯片重叠的区域的一部分上的第一树脂层; 以及安装在半导体芯片和第一树脂层之间的第二树脂层。 焊盘与暴露在第一树脂层上的布线图案的一部分相对并耦合; 并且布线基板的线膨胀系数大于半导体芯片的线膨胀系数，布线基板的弹性模量低于半导体芯片的弹性模量，并且第一树脂层的线膨胀系数大于第二树脂层的线膨胀系数 树脂层。 第一树脂层的弹性模量低于第二树脂层的弹性模量。

公开(公告)号：US20080285247A1

公开(公告)日：2008-11-20

申请号：US12091094

申请日：2006-10-24

Applicant: Qing Ji ,  Chew B. Chan ,  Hwang K. Yun ,  Renzhe Zhao ,  Weitong Shi

Inventor： Qing Ji ,  Chew B. Chan ,  Hwang K. Yun ,  Renzhe Zhao ,  Weitong Shi

IPC: H05K7/00 ,  C08L63/00 ,  H01L21/00

CPC classification number: C08G59/68 ,  C08G59/226 ,  C08K3/36 ,  C08K5/1515 ,  C08L63/00 ,  C08L2205/02 ,  H01L21/563 ,  H01L23/293 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83192 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H05K3/284 ,  H05K3/305 ,  H05K2201/0209 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2203/176 ,  Y02P70/613 ,  Y10T428/31511 ,  Y10T428/31515 ,  H01L2924/00 ,  H01L2924/3512

Abstract: This invention relates to the thermosetting resin compositions useful for mounting onto a circuit board semiconductor devices, such as chip size or chip scale packages (“CSPs”), ball grid arrays (“BGAs”), land grid arrays (“LGAs”) and the like, each of which having a semiconductor chip, such as large scale integration (“LSI”), on a carrier substrate. Similarly, the compositions are useful for mounting onto circuit board semiconductor chips themselves. Reaction products of the compositions of this invention are controllably reworkable when subjected to appropriate conditions. And significantly, unlike many commercial rapid curing underfill sealants (“snap cure underfills”), the inventive compositions possess an exotherm under 300 J/g or demonstrate package stability at 55° C. for 7 days, and therefore do not require special packaging to be transported by air courier, or special approval from international transportation authorities, such as the U.S. Department of Transportation, to permit such air transport. The inventive compositions possess an exotherm under 300 J/g and/or demonstrate package stability at 55° C. for 7 days and therefore do not require special packaging to be transported by air courier, or special approval from international transportation authorities, such as the U.S. Department of Transportation, to permit such air transport.

Abstract translation: 本发明涉及可用于安装到诸如芯片尺寸或芯片尺寸封装（“CSP”），球栅阵列（“BGAs”），焊盘网格阵列（“LGAs”）和电路板半导体器件 其中每个在载体基板上具有诸如大规模集成（“LSI”）的半导体芯片。 类似地，组合物可用于将其自身安装到电路板半导体芯片上。 当经受适当条件时，本发明组合物的反应产物是可控制的可再加工的。 并且显着地，与许多商业快速固化底部填充密封剂（“快速固化底部填充剂”）不同，本发明组合物具有300J / g以下的放热或在55℃下显示包装稳定性7天，因此不需要特殊包装 由航空快递运送，或由美国交通运输部等国际运输部门特别批准，允许这样的航空运输。 本发明的组合物具有低于300J / g的放热和/或在55℃下展示包装稳定性7天，因此不需要特殊包装通过空运快递运输，或者得到国际运输当局的特别批准，例如 美国交通部允许这样的航空运输。

公开(公告)号：US07452197B2

公开(公告)日：2008-11-18

申请号：US11656378

申请日：2007-01-23

Applicant: Kenya Wada ,  Jun Onoshiro ,  Kouji Hiraseko

Inventor： Kenya Wada ,  Jun Onoshiro ,  Kouji Hiraseko

IPC: B29C65/40

CPC classification number: G02F1/13452 ,  B05C5/0208 ,  G02F2202/28 ,  H05K3/284 ,  H05K3/305 ,  H05K3/361 ,  H05K2201/10977 ,  H05K2203/0126 ,  H05K2203/1572

Abstract: On an application stage of resin are provided two (2) sets of dispensers 20 and 40. The one dispenser 20 supplies the resin directing to an upper side corner on a liquid crystal cell 1, while the other dispenser 40 directing to a lower side corner thereon. The dispenser 40 has a syringe 41 and a needle-like nozzle 42, and the needle-like nozzle 42 emits the resin, directing upward obliquely, onto the lower side corner. Thereby, the resin can be supplied between an edge portion of a lower substrate and a lower surface of a connecting board, but without turning over the panel for display, such as, a liquid crystal cell, etc.

Abstract translation: 在树脂的施加阶段设置两（2）套分配器20和40。 一个分配器20将引导到液晶单元1上的上角的树脂供给，而另一个分配器40指向其下侧角。 分配器40具有注射器41和针状喷嘴42，并且针状喷嘴42将树脂向上倾斜向上引导到下侧角。 因此，可以在下基板的边缘部分和连接板的下表面之间提供树脂，但是不转动诸如液晶单元等的用于显示的面板。

公开(公告)号：US20080279408A1

公开(公告)日：2008-11-13

申请号：US12149629

申请日：2008-05-06

Applicant: Noriko Matsui

Inventor： Noriko Matsui

IPC: H04R11/04

CPC classification number: H05K3/3405 ,  H04R1/08 ,  H05K3/3421 ,  H05K2201/10287 ,  H05K2201/10977 ,  H05K2203/1311

Abstract: In a gooseneck microphone in which a support pipe is capable of extending and contracting, and accordingly a microphone cord extension/contraction part is provided in an output module section, the microphone cord soldered part on a circuit board is prevented from being rubbed by the microphone cord extension/contraction part. The gooseneck microphone includes the support pipe that includes a telescopic pipe and supports a condenser microphone unit on the upper end side thereof, the output module section 30 that is connected to the lower end of the support pipe via a connector 23 at the upper end of a shield case incorporating the circuit board 32, and a microphone cord 40 one end of which is connected to the condenser microphone unit and the other end 40b of which is pulled out into the output module section 30 through the support pipe and a connector 23 and is soldered to the circuit board 32, and a cord extension/contraction part 41 that extends and contracts along with the extension and contraction of the support pipe is provided on the other end 40b side of the microphone cord in the output module section 30. In the gooseneck microphone, the circuit board 32 is provided with a covering member 50 for covering at least a soldered part S of the microphone cord 40.

Abstract translation: 在其中支撑管能够伸缩的鹅颈式麦克风中，并且相应地在输出模块部分中设置麦克风线延伸/收缩部分，防止电路板上的麦克风线焊接部分被麦克风摩擦 线延伸/收缩部分。 鹅颈麦克风包括支撑管，其包括伸缩管并在其上端侧支撑电容式麦克风单元，输出模块部30经由连接器23在上端连接到支撑管的下端 包括电路板32的屏蔽盒和麦克风线40，其一端连接到电容麦克风单元，另一端40b通过支撑管被拉出到输出模块部分30中，连接器23 并且被焊接到电路板32，并且在输出模块部分30中的麦克风线的另一端40b侧上设置有延伸和收缩支撑管的延伸和收缩的电缆延伸/收缩部分41 在鹅颈麦克风中，电路板32设置有用于覆盖麦克风线40的至少焊接部分S的覆盖部件50。

公开(公告)号：US20080277803A1

公开(公告)日：2008-11-13

申请号：US12174273

申请日：2008-07-16

Applicant: Yoshiharu OGATA

Inventor： Yoshiharu OGATA

IPC: H01L23/52

CPC classification number: H05K3/305 ,  H01L21/563 ,  H01L23/3128 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/29007 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K1/0271 ,  H05K3/3452 ,  H05K2201/09772 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2924/00014

Abstract: A semiconductor device comprises a wiring substrate including a wiring pattern; a semiconductor chip installed on the wiring substrate, including a plurality of pads formed on a surface of the semiconductor chip, which opposes the wiring substrate; a first resin layer covering over a part of the wiring pattern within a region of overlapping the semiconductor chip; and a second resin layer installed between the semiconductor chip and the first resin layer. The pads are oppose to and coupled with a part of the wiring pattern exposed over the first resin layer; and the linear expansion coefficient of the wiring substrate is larger than that of the semiconductor chip, the elastic modulus of the wiring substrate is lower than that of the semiconductor chip and the linear expansion coefficient of the first resin layer is larger than that of the second resin layer. The elastic modulus of the first resin layer is lower than that of the second resin layer.

Abstract translation: 半导体器件包括：布线基板，其包括布线图案; 安装在所述布线基板上的半导体芯片，包括与所述布线基板相对的形成在所述半导体芯片的表面上的多个焊盘; 覆盖所述布线图案的与所述半导体芯片重叠的区域的一部分上的第一树脂层; 以及安装在半导体芯片和第一树脂层之间的第二树脂层。 焊盘与暴露在第一树脂层上的布线图案的一部分相对并耦合; 并且布线基板的线膨胀系数大于半导体芯片的线膨胀系数，布线基板的弹性模量低于半导体芯片的弹性模量，并且第一树脂层的线膨胀系数大于第二树脂层的线膨胀系数 树脂层。 第一树脂层的弹性模量低于第二树脂层的弹性模量。