公开(公告)号：US20190252367A1

公开(公告)日：2019-08-15

申请号：US16391057

申请日：2019-04-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Te Lin ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Pin-Dai Sue ,  Li-Chun Tien

IPC: H01L27/02 ,  G06F17/50 ,  H01L27/092 ,  H01L27/088

Abstract: An integrated circuit includes at least one first active region, at least one second active region adjacent to the first active region, and a plurality of third active regions. The first active region and the second active region are staggered. The third active regions are present adjacent to the first active region, wherein the third active regions are substantially aligned with each other.

公开(公告)号：US12148505B2

公开(公告)日：2024-11-19

申请号：US18362685

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: G11C8/14 ,  H01L21/822 ,  H10B51/20 ,  H10B99/00

Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line extending from a first edge of the memory array in a first direction, the first word line having a length less than a length of a second edge of the memory array perpendicular to the first edge of the memory array; a second word line extending from a third edge of the memory array opposite the first edge of the memory array, the second word line extending in the first direction, the second word line having a length less than the length of the second edge of the memory array; a memory film contacting the first word line; and an OS layer contacting a first source line and a first bit line, the memory film being disposed between the OS layer and the first word line.

公开(公告)号：US12127489B2

公开(公告)日：2024-10-22

申请号：US18170947

申请日：2023-02-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-Yen Peng ,  Hui-Hsien Wei ,  Wei-Chih Wen ,  Pin-Ren Dai ,  Chien-Min Lee ,  Han-Ting Tsai ,  Jyu-Horng Shieh ,  Chung-Te Lin

IPC: H10B63/00 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10N70/884 ,  H10B61/22 ,  H10B63/30 ,  H10B63/82 ,  H10B63/84 ,  H10N50/01 ,  H10N50/80 ,  H10N70/023 ,  H10N70/063 ,  H10N70/24 ,  H10N70/245 ,  H10N70/826 ,  H10N70/8416 ,  H10N70/8833

Abstract: An IC structure comprises a substrate, a first dielectric structure, a second dielectric structure, a first via structure, and a memory cell structure. The substrate comprises a memory region and a logic region. The first dielectric structure is over the memory region. The second dielectric structure laterally extends from the first dielectric structure to over the logic region. The second dielectric structure has a thickness less than a thickness of the first dielectric structure. The first via structure extends through the first dielectric structure. A top segment of the first via structure is higher than a top surface of the first dielectric structure. The first memory cell structure is over the first via structure.

公开(公告)号：US20240138152A1

公开(公告)日：2024-04-25

申请号：US18401988

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Cheng Yang ,  Meng-Han Lin ,  Sheng-Chen Wang ,  Han-Jong Chia ,  Chung-Te Lin

IPC: H10B51/20 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/522 ,  H10B51/30

CPC classification number: H10B51/20 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76871 ,  H01L21/76877 ,  H01L23/5226 ,  H10B51/30

Abstract: In accordance with embodiments, a memory array is formed with a multiple patterning process. In embodiments a first trench is formed within a multiple layer stack and a first conductive material is deposited into the first trench. After the depositing the first conductive material, a second trench is formed within the multiple layer stack, and a second conductive material is deposited into the second trench. The first conductive material and the second conductive material are etched.

公开(公告)号：US20240105725A1

公开(公告)日：2024-03-28

申请号：US18193087

申请日：2023-03-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gerben Doornbos ,  Marcus Johannes Henricus Van Dal ,  Szuya Liao ,  Chung-Te Lin

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7851

Abstract: An integrated circuit includes a complimentary field effect transistor (CFET). The CFET includes a first transistor and a second transistor stacked vertically. A conductive via extends vertically from a first source/drain region of the first transistor past the second transistor. The second transistor includes an asymmetric second source/drain region. The asymmetry of the second source/drain region helps ensure that the second source/drain region does not contact the conductive via.

公开(公告)号：US11769815B2

公开(公告)日：2023-09-26

申请号：US17319461

申请日：2021-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Rainer Yen-Chieh Huang ,  Hai-Ching Chen ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L29/06 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78 ,  H01L29/417 ,  H10B51/20 ,  H10B51/30

CPC classification number: H01L29/516 ,  H01L29/40111 ,  H01L29/41725 ,  H01L29/6656 ,  H01L29/6684 ,  H01L29/78391 ,  H10B51/20 ,  H10B51/30

Abstract: The present disclosure relates to an integrated circuit (IC) chip including a memory cell with a carrier barrier layer for threshold voltage tuning. The memory cell may, for example, include a gate electrode, a ferroelectric structure, and a semiconductor structure. The semiconductor structure is vertically stacked with the gate electrode and the ferroelectric structure, and the ferroelectric structure is between the gate electrode and the semiconductor structure. A pair of source/drain electrodes is laterally separated and respectively on opposite sides of the gate electrode, and a carrier barrier layer separates the source/drain electrodes from the semiconductor structure.

公开(公告)号：US11729990B2

公开(公告)日：2023-08-15

申请号：US17168361

申请日：2021-02-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Rainer Yen-Chieh Huang ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H10B51/30 ,  H01L23/522 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L29/786 ,  H10B51/00

CPC classification number: H10B51/30 ,  H01L23/5226 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/66765 ,  H01L29/7869 ,  H01L29/78391 ,  H01L29/78648 ,  H01L29/78669 ,  H01L29/78678 ,  H01L29/78687 ,  H01L29/78693 ,  H10B51/00

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a gate electrode over a substrate, and a gate dielectric layer arranged over the gate electrode. The gate dielectric layer includes a ferroelectric material. An active structure is arranged over the gate dielectric layer and includes a semiconductor material. A source contact and a drain contact are arranged over the active structure. A capping structure is arranged between the source and drain contacts and over the active structure. The capping structure includes a first metal material.

公开(公告)号：US11729983B2

公开(公告)日：2023-08-15

申请号：US17304049

申请日：2021-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chih Lai ,  Chung-Te Lin

IPC: H10B43/40 ,  H01L21/768 ,  H01L21/311 ,  H01L29/51 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L21/28 ,  H10B43/27

CPC classification number: H10B43/40 ,  H01L21/31111 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/5226 ,  H01L23/53257 ,  H01L29/40117 ,  H01L29/513 ,  H01L29/518 ,  H10B43/27

Abstract: A semiconductor device and method of forming thereof that includes a transistor of a peripheral circuit on a substrate. A first interconnect structure such as a first access line is formed over the transistor. A via extends above the first access line. A plurality of memory cell structures is formed over the interconnect structure and the via. A second interconnect structure, such as a second access line, is formed over the memory cell structure. The first access line is coupled to a first memory cell of the plurality of memory cell structures and second access line is coupled to a second memory cell of the plurality of memory cell structures.

公开(公告)号：US11723291B2

公开(公告)日：2023-08-08

申请号：US17218324

申请日：2021-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mauricio Manfrini ,  Chung-Te Lin ,  Gerben Doornbos ,  Marcus Johannes Henricus van Dal

IPC: H01L21/768 ,  H10N70/00 ,  G11C13/00 ,  H10B63/00

CPC classification number: H10N70/823 ,  G11C13/0007 ,  G11C13/0011 ,  H10B63/30 ,  H10N70/021 ,  H10N70/841 ,  H10N70/883

Abstract: Some embodiments relate to an integrated chip including a memory device. The memory device includes a bottom electrode disposed over a semiconductor substrate. An upper electrode is disposed over the bottom electrode. An intercalated metal/dielectric structure is sandwiched between the bottom electrode and the upper electrode. The intercalated metal/dielectric structure comprises a lower dielectric layer over the bottom electrode, an upper dielectric layer over the lower dielectric layer, and a first metal layer separating the upper dielectric layer from the lower dielectric layer.

公开(公告)号：US11723210B2

公开(公告)日：2023-08-08

申请号：US17333300

申请日：2021-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsu Ching Yang ,  Feng-Cheng Yang ,  Sheng-Chih Lai ,  Yu-Wei Jiang ,  Kuo-Chang Chiang ,  Hung-Chang Sun ,  Chen-Jun Wu ,  Chung-Te Lin

IPC: H10B51/20 ,  H10B51/30

CPC classification number: H10B51/20 ,  H10B51/30

Abstract: In some embodiments, the present disclosure relates to a method for forming a memory device, including forming a plurality of word line stacks respectively including a plurality of word lines alternatingly stacked with a plurality of insulating layers over a semiconductor substrate, forming a data storage layer along opposing sidewalls of the word line stacks, forming a channel layer along opposing sidewalls of the data storage layer, forming an inner insulating layer between inner sidewalls of the channel layer and including a first dielectric material, performing an isolation cut process including a first etching process through the inner insulating layer and the channel layer to form an isolation opening, forming an isolation structure filling the isolation opening and including a second dielectric material, performing a second etching process through the inner insulating layer on opposing sides of the isolation structure to form source/drain openings, and forming source/drain contacts in the source/drain openings.