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    Chemical mechanical polishing apparatus
    152.
    发明申请
    Chemical mechanical polishing apparatus 失效

    公开(公告)号：US20050048875A1

    公开(公告)日：2005-03-03

    申请号：US10850688

    申请日：2004-05-21

    Applicant: Ja-Eung Koo ,  Jong-Won Lee ,  Sung-Bae Lee ,  Duk-Ho Hong ,  Sang-Rok Hah ,  Hong-Seong Son

    Inventor： Ja-Eung Koo ,  Jong-Won Lee ,  Sung-Bae Lee ,  Duk-Ho Hong ,  Sang-Rok Hah ,  Hong-Seong Son

    IPC: B24B37/02 ,  B24B37/04 ,  B24B49/10 ,  B24B49/14 ,  B24B49/00 ,  B24B1/00

    CPC classification number: B24B37/013 ,  B24B49/10 ,  B24B49/14

    Abstract: There is provided a chemical mechanical polishing apparatus, which may include a polishing table rotated by a polishing table motor and having a pad thereon, a carrier head located above the polishing table to be rotatable by the driving of a carrier head motor and having a wafer located under the bottom thereof, a slurry supplier for supplying a slurry to the upper portion of the polishing table, a first polishing end point detector for detecting a polishing end point through the temperature change of the temperature sensor, at least one temperature sensor for detecting the temperature of a polishing region (the wafer, the pad, and the slurry), and a second polishing end point detector for detecting a polishing end point from the changes of load current, voltage, and resistance of the carrier head motor. Further, instead of the second polishing end point detector, an optical signal polishing end point detector may be employed, for detecting the polishing end point by the light illuminated on the wafer and reflected from the wafer.

    Method of forming metal interconnection using plating and semiconductor device manufactured by the method
    154.
    发明授权
    Method of forming metal interconnection using plating and semiconductor device manufactured by the method 有权
    使用该方法制造的使用电镀和半导体器件形成金属互连的方法

    公开(公告)号：US06610596B1

    公开(公告)日：2003-08-26

    申请号：US09662120

    申请日：2000-09-14

    Applicant: Jong-won Lee ,  Bo-un Yoon ,  Kun-tack Lee ,  Sang-rok Hah

    Inventor： Jong-won Lee ,  Bo-un Yoon ,  Kun-tack Lee ,  Sang-rok Hah

    IPC: H01L2144

    CPC classification number: H01L21/7684 ,  H01L21/76879

    Abstract: A method is provided for forming a metal interconnection using a plating process, which can improve the throughput and reliability of semiconductor devices by decreasing the required polishing in a chemical mechanical polishing process. A semiconductor device manufactured by this method is also provided. In the method of forming a metal interconnection, a recess region is formed in a portion of an insulation layer formed over a substrate, i.e., where a metal interconnection layer will be formed. A diffusion prevention layer is formed over the substrate, the insulation layer, and the recess region. Then, a metal seed layer is formed over the diffusion prevention layer only in the recess region using a chemical mechanical polishing process or an etch back process. A conductive plating layer is then formed on the metal seed layer only in the recess region. Thereafter, surface polarization is performed to form a metal interconnection layer in the recess region. The plating layer may be formed after forming the seed layer only in the bottom portion of the recess region.

    Abstract translation: 提供了一种使用电镀工艺形成金属互连的方法，其可以通过减少化学机械抛光工艺中所需的抛光来提高半导体器件的生产能力和可靠性。 还提供了通过该方法制造的半导体器件。 在形成金属互连的方法中，在形成在基板上的绝缘层的一部分中，即将形成金属互连层的区域中形成凹陷区域。 在基板，绝缘层和凹部区域上形成扩散防止层。 然后，使用化学机械抛光工艺或回蚀工艺，仅在凹陷区域中在扩散防止层上形成金属种子层。 然后在金属种子层上仅在凹陷区域中形成导电镀层。 此后，进行表面极化以在凹部区域中形成金属互连层。 可以在仅在凹部的底部形成种子层之后形成镀层。

    Electroluminescence device and method for manufacturing the same
    155.
    发明授权
    Electroluminescence device and method for manufacturing the same 有权

    公开(公告)号：US06579631B2

    公开(公告)日：2003-06-17

    申请号：US09893561

    申请日：2001-06-29

    Applicant: Jong Won Lee

    Inventor： Jong Won Lee

    IPC: H05B3312

    CPC classification number: H05B33/20 ,  H05B33/10 ,  H05B33/12 ,  Y10S428/917 ,  Y10T428/2991

    Abstract: An electroluminescence device and a method for manufacturing the same minimize the process steps and the manufacturing cost, and allow a sufficiently high light-emitting effect under a low driving voltage. The electroluminescence device includes a substrate, a lower electrode layer formed on the substrate, a light-emitting layer formed on the lower electrode layer, an upper electrode layer formed on the light-emitting layer, and a passivation layer formed on the upper electrode layer. The method for manufacturing an electroluminescence device includes the steps of forming a lower electrode layer on a substrate, forming a light-emitting layer on the lower electrode layer, forming an upper electrode layer on the light-emitting layer, and forming a passivation layer on the upper electrode.

    Memory array plane select and methods
    156.
    发明授权
    Memory array plane select and methods 有权
    内存阵列平面选择和方法

    公开(公告)号：US09117503B2

    公开(公告)日：2015-08-25

    申请号：US13597520

    申请日：2012-08-29

    Applicant: Jong-Won Lee ,  Gianpaolo Spadini

    Inventor： Jong-Won Lee ,  Gianpaolo Spadini

    IPC: G11C13/04 ,  G11C8/12 ,  G11C5/02 ,  G11C13/00 ,  G11C11/16

    CPC classification number: G11C13/0023 ,  G11C5/025 ,  G11C8/12 ,  G11C11/1653 ,  G11C11/1659 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/0069 ,  G11C2213/71

    Abstract: Memory arrays and methods of forming the same are provided. An example memory array can include at least one plane having a plurality of memory cells arranged in a matrix and a plurality of plane selection devices. Groups of the plurality of memory cells are communicatively coupled to a respective one of a plurality of plane selection devices. A decode logic having elements is formed in a substrate material and communicatively coupled to the plurality of plane selection devices. The plurality of memory cells and the plurality of plane selection devices are not formed in the substrate material.

    Abstract translation: 提供了存储器阵列及其形成方法。 示例性存储器阵列可以包括具有以矩阵形式布置的多个存储单元和多个平面选择装置的至少一个平面。 多个存储器单元的组通信地耦合到多个平面选择装置中的相应一个。 具有元件的解码逻辑形成在衬底材料中并且通信地耦合到多个平面选择装置。 多个存储单元和多个平面选择装置不形成在基板材料中。

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