公开(公告)号：US09583396B2

公开(公告)日：2017-02-28

申请号：US14777730

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： Niti Goel ,  Benjamin Chu-Kung ,  Sansaptak Dasgupta ,  Niloy Mukherjee ,  Matthew V. Metz ,  Van H. Le ,  Jack T. Kavalieros ,  Robert S. Chau ,  Ravi Pillarisetty

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L21/823807 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02463 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/02647 ,  H01L21/76224 ,  H01L21/76248 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L29/66795

Abstract: Electronic device fins may be formed by epitaxially growing a first layer of material on a substrate surface at a bottom of a trench formed between sidewalls of shallow trench isolation (STI) regions. The trench height may be at least 1.5 times its width, and the first layer may fill less than the trench height. Then a second layer of material may be epitaxially grown on the first layer in the trench and over top surfaces of the STI regions. The second layer may have a second width extending over the trench and over portions of top surfaces of the STI regions. The second layer may then be patterned and etched to form a pair of electronic device fins over portions of the top surfaces of the STI regions, proximate to the trench. This process may avoid crystalline defects in the fins due to lattice mismatch in the layer interfaces.

Abstract translation: 可以通过在形成在浅沟槽隔离（STI）区域的侧壁之间的沟槽的底部的衬底表面上外延生长第一层材料来形成电子器件鳍。 沟槽高度可以是其宽度的至少1.5倍，并且第一层可以填充小于沟槽高度。 然后可以在沟槽中的第一层和STI区域的顶表面上外延生长第二层材料。 第二层可以具有在沟槽上延伸的第二宽度和STI区域的顶表面的上部。 然后可以对第二层进行图案化和蚀刻，以在靠近沟槽的STI区域的顶表面的部分上形成一对电子器件散热片。 该过程可以避免由于层界面中的晶格失配导致的鳍片中的晶体缺陷。

公开(公告)号：US09478635B2

公开(公告)日：2016-10-25

申请号：US14924643

申请日：2015-10-27

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Been-Yih Jin ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Roza Kotlyar ,  Willy Rachmady ,  Niloy Mukherjee ,  Gilbert Dewey ,  Robert S. Chau

IPC: H01L29/66 ,  H01L29/267 ,  H01L21/283 ,  H01L29/15 ,  H01L21/02 ,  H01L29/165 ,  H01L29/778 ,  H01L29/775 ,  H01L29/51

CPC classification number: H01L27/092 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/283 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66522 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/7782

Abstract: A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.

公开(公告)号：US09461141B2

公开(公告)日：2016-10-04

申请号：US14831307

申请日：2015-08-20

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Willy Rachmady ,  Van H. Le ,  Gilbert Dewey ,  Niloy Mukherjee ,  Matthew V. Metz ,  Han Wui Then ,  Marko Radosavljevic

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L23/485 ,  H01L29/775 ,  H01L29/78 ,  B82Y99/00 ,  B82Y40/00

CPC classification number: H01L29/41791 ,  B82Y40/00 ,  B82Y99/00 ,  G11C7/02 ,  H01L23/485 ,  H01L23/535 ,  H01L27/115 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696 ,  H01L2029/7858 ,  H01L2924/0002 ,  Y10S977/762 ,  Y10S977/89 ,  H01L2924/00

Abstract: Embodiments of the present disclosure provide contact techniques and configurations for reducing parasitic resistance in nanowire transistors. In one embodiment, an apparatus includes a semiconductor substrate, an isolation layer formed on the semiconductor substrate, a channel layer including nanowire material formed on the isolation layer to provide a channel for a transistor, and a contact coupled with the channel layer, the contact being configured to surround, in at least one planar dimension, nanowire material of the channel layer and to provide a source terminal or drain terminal for the transistor.

公开(公告)号：US20160268407A1

公开(公告)日：2016-09-15

申请号：US15164754

申请日：2016-05-25

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Mantu K. Hudait ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Willy Rachmady ,  Niloy Mukherjee ,  Robert S. Chau

IPC: H01L29/778 ,  H01L29/201 ,  H01L29/66 ,  H01L29/423 ,  H01L29/40 ,  H01L29/15 ,  H01L29/205

CPC classification number: H01L29/7784 ,  H01L29/151 ,  H01L29/155 ,  H01L29/201 ,  H01L29/205 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/41775 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/775 ,  H01L29/7783 ,  H01L29/78

Abstract: Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.

公开(公告)号：US20160204036A1

公开(公告)日：2016-07-14

申请号：US14777730

申请日：2013-06-28

Applicant: INTEL CORPORATION

Inventor： Niti Goel ,  Benjamin Chu-Kung ,  Sansaptak Dasgupta ,  Niloy Mukherjee ,  Matthew V. Metz ,  Van H. Le ,  Jack T. Kavalieros ,  Robert S. Chau ,  Ravi Pillarisetty

IPC: H01L21/8238 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L21/823807 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02463 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/02647 ,  H01L21/76224 ,  H01L21/76248 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L29/66795

Abstract: Electronic device fins may be formed by epitaxially growing a first layer of material on a substrate surface at a bottom of a trench formed between sidewalls of shallow trench isolation (STI) regions. The trench height may be at least 1.5 times its width, and the first layer may fill less than the trench height. Then a second layer of material may be epitaxially grown on the first layer in the trench and over top surfaces of the STI regions. The second layer may have a second width extending over the trench and over portions of top surfaces of the STI regions. The second layer may then be patterned and etched to form a pair of electronic device fins over portions of the top surfaces of the STI regions, proximate to the trench. This process may avoid crystalline defects in the fins due to lattice mismatch in the layer interfaces.

Abstract translation: 可以通过在形成在浅沟槽隔离（STI）区域的侧壁之间的沟槽的底部的衬底表面上外延生长第一层材料来形成电子器件鳍。 沟槽高度可以是其宽度的至少1.5倍，并且第一层可以填充小于沟槽高度。 然后可以在沟槽中的第一层和STI区域的顶表面上外延生长第二层材料。 第二层可以具有在沟槽上延伸的第二宽度和STI区域的顶表面的上部。 然后可以对第二层进行图案化和蚀刻，以在靠近沟槽的STI区域的顶表面的部分上形成一对电子器件散热片。 该过程可以避免由于层界面中的晶格失配导致的鳍片中的晶体缺陷。

公开(公告)号：US20160064540A1

公开(公告)日：2016-03-03

申请号：US14935346

申请日：2015-11-06

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Marko Radosavljevic ,  Uday Shah ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Robert S. Chau

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/423 ,  H01L21/02 ,  H01L21/311 ,  H01L29/66 ,  H01L29/205

CPC classification number: H01L29/7787 ,  H01L21/02241 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/02258 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/268 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/31111 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/365 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/512 ,  H01L29/518 ,  H01L29/66462

Abstract: III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.

公开(公告)号：US09219079B2

公开(公告)日：2015-12-22

申请号：US14581722

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Sanaz Gardner ,  Seung Hoon Sung ,  Robert S. Chau

IPC: H01L29/78 ,  H01L27/12 ,  H01L29/80 ,  H01L29/20 ,  H01L29/66 ,  H01L21/02 ,  H01L21/285 ,  H01L21/84 ,  H01L29/06 ,  H01L29/201 ,  H01L29/778

CPC classification number: H01L29/2003 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/0228 ,  H01L21/0254 ,  H01L21/283 ,  H01L21/28575 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/201 ,  H01L29/42356 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/802

Abstract: A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin.

Abstract translation: III-N半导体沟道形成在形成于诸如翅片侧壁的硅模板结构的（111）或（110）表面上的III-N过渡层上。 在实施例中，硅鳍具有与更适应的种子层的III-N外延膜厚度相当的宽度，允许更低的缺陷密度和/或降低的外延膜厚度。 在实施例中，过渡层是GaN，并且半导体沟道包括铟（In）以增加从硅片的导带偏移。 在其它实施例中，鳍是牺牲性的，并且在晶体管制造期间被去除或氧化，或以其它方式转换为电介质结构。 在采用牺牲散热片的某些实施例中，III-N过渡层和半导体通道是基本上纯的GaN，允许击穿电压高于在硅片存在时可持续的击穿电压。

公开(公告)号：US20150171205A1

公开(公告)日：2015-06-18

申请号：US14630541

申请日：2015-02-24

Applicant: Intel Corporation

Inventor： HAN WUI THEN ,  Marko Radosavljevic ,  Uday Shah ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Robert S. Chau

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/423 ,  H01L21/306 ,  H01L21/02 ,  H01L21/311 ,  H01L29/66 ,  H01L29/205

CPC classification number: H01L29/7787 ,  H01L21/02241 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/02258 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/268 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/31111 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/365 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/512 ,  H01L29/518 ,  H01L29/66462

Abstract: III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.

Abstract translation: 具有凹入栅极的III-N晶体管。 外延堆叠包括掺杂的III-N源极/漏极层和设置在源/漏层和II​​I-N沟道层之间的III-N蚀刻停止层。 蚀刻工艺，例如利用光化学氧化，选择性地蚀刻蚀刻停止层上的源极/漏极层。 栅电极设置在蚀刻停止层上方以形成凹入栅III-N HEMT。 蚀刻停止层的至少一部分可以用氧化蚀刻停止层上的栅电极氧化，用于包括III-N氧化​​物的凹陷栅III-N MOS-HEMT。 可以在氧化的蚀刻停止层上形成高k电介质，并在高k电介质上形成栅电极，以形成具有复合栅电介质叠层的凹陷栅III-N MOS-HEMT。

公开(公告)号：US09048266B2

公开(公告)日：2015-06-02

申请号：US13956685

申请日：2013-08-01

Applicant: INTEL CORPORATION

Inventor： Ravi Pillarisetty ,  Mantu Hudait ,  Been-Yih Jin ,  Benjamin Chu-Kung ,  Robert Chau

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/161 ,  H01L29/36

CPC classification number: H01L29/66977 ,  H01L29/1083 ,  H01L29/161 ,  H01L29/365 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/7781

Abstract: Embodiments of an apparatus and methods of providing a quantum well device for improved parallel conduction are generally described herein. Other embodiments may be described and claimed.

Abstract translation: 本文通常描述了提供用于改进的并联传导的量子阱装置的装置和方法的实施例。 可以描述和要求保护其他实施例。

公开(公告)号：US20240055531A1

公开(公告)日：2024-02-15

申请号：US18494384

申请日：2023-10-25

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Shriram Shivaraman ,  Benjamin Chu-Kung ,  Yih Wang ,  Tahir Ghani

IPC: H01L29/786 ,  H01L29/08 ,  H01L29/04 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  H01L29/423 ,  H10B12/00

CPC classification number: H01L29/78642 ,  H01L29/78648 ,  H01L29/0847 ,  H01L29/04 ,  H01L29/6675 ,  H01L29/78696 ,  H01L29/1037 ,  H01L21/02647 ,  H01L29/6656 ,  H01L29/42384 ,  H10B12/05 ,  H10B12/50 ,  H10B12/315 ,  H01L21/31116

Abstract: Disclosed herein are dual gate trench shaped thin film transistors and related methods and devices. Exemplary thin film transistor structures include a non-planar semiconductor material layer having a first portion extending laterally over a first gate dielectric layer, which is over a first gate electrode structure, and a second portion extending along a trench over the first gate dielectric layer, a second gate electrode structure at least partially within the trench, and a second gate dielectric layer between the second gate electrode structure and the first portion.