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222 条记录 (耗时 0.035 秒)

    BACK-GATE DECODE PERSONALIZATION
    151.
    发明申请
    BACK-GATE DECODE PERSONALIZATION 失效
    后门解码个人化

    公开(公告)号：US20090219778A1

    公开(公告)日：2009-09-03

    申请号：US12039233

    申请日：2008-02-28

    申请人： Kerry Bernstein ,  Wilfried Haensch

    发明人： Kerry Bernstein ,  Wilfried Haensch

    IPC分类号： G11C8/10

    CPC分类号： G11C8/10

    摘要： A novel methodology for the construction and operation of logical circuits and gates that makes use of and contact to a fourth (4th) terminal (substrates/bodies) of MOSFET devices is implemented by the present invention to realize a novel decode personalization. The novel construction and operation of the decode personalization provides for maintaining body-contacted MOSFET devices at a lower threshold voltage (VTh) when actively on (to increase overdrive and performance), and at a higher relative threshold voltage when off (to reduce leakage power). Because the threshold potential of a transistor moves inversely to its body potential, the body of each device is tied to the inverse of the device's drain voltage to achieve such a desirable threshold potential modulation effect for improved device, circuit, gate, decode personalization and logical family operation.

    摘要翻译： 通过本发明实现了利用和接触MOSFET器件的第四（4）端子（衬底/体）的逻辑电路和栅极的构造和操作的新颖方法，以实现新颖的解码个性化。 解码个性化的新颖结构和操作提供了当主动接通（以增加过驱动和性能）时保持身体接触的MOSFET器件处于较低阈值电压（VTh），并且在关闭时处于较高的相对阈值电压（以减少漏电功率 ）。 由于晶体管的阈值电位与其电位相反，所以每个器件的主体与器件的漏极电压相反，以达到改善器件，电路，栅极，解码个性化和逻辑的理想阈值电位调制效应 家庭经营。

    Multicore Processor Having Storage for Core-Specific Operational Data
    155.
    发明申请
    Multicore Processor Having Storage for Core-Specific Operational Data 有权
    具有存储核心特定操作数据的多核处理器

    公开(公告)号：US20090055826A1

    公开(公告)日：2009-02-26

    申请号：US11842206

    申请日：2007-08-21

    申请人： Kerry Bernstein ,  Nazmul Habib ,  Norman J. Rohrer

    发明人： Kerry Bernstein ,  Nazmul Habib ,  Norman J. Rohrer

    IPC分类号： G06F9/46 ,  G06F9/30

    CPC分类号： G06F9/3851 ,  G06F9/3891

    摘要： An integrated circuit includes a plurality of processor cores and a readable non-volatile memory that stores information expressive of at least one operating characteristic for each of the plurality of processor cores. Also disclosed is a method to operate a data processing system, where the method includes providing a multicore processor that contains a plurality of processor cores and a readable non-volatile memory that stores information, determined during a testing operation, that is indicative of at least a maximum operating frequency for each of the plurality of processor cores. The method further includes operating a scheduler coupled to an operating system and to the multicore processor, where the scheduler is operated to be responsive at least in part to information read from the memory to schedule the execution of threads to individual ones of the processor cores for a more optimal usage of energy.

    摘要翻译： 集成电路包括多个处理器核心和可读非易失性存储器，其存储表示多个处理器核心中的每一个的至少一个操作特性的信息。 还公开了一种操作数据处理系统的方法，其中所述方法包括提供包含多个处理器核心的多核处理器和存储在测试操作期间确定的信息的可读非易失性存储器，其指示至少 用于所述多个处理器核心中的每一个的最大工作频率。 所述方法还包括操作耦合到操作系统和多核处理器的调度器，其中调度器被操作以至少部分地响应于从存储器读取的信息，以调度到处理器核心中的各个处理器核心的线程的执行 更优化的能量使用。

    Determining history state of data based on state of partially depleted silicon-on-insulator
    156.
    发明授权
    Determining history state of data based on state of partially depleted silicon-on-insulator 失效
    基于部分耗尽的绝缘体上硅的状态确定数据的历史状态

    公开(公告)号：US07460422B2

    公开(公告)日：2008-12-02

    申请号：US11279507

    申请日：2006-04-12

    申请人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvis ,  Sebastian T. Ventrone ,  Keith R. Williams

    发明人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvis ,  Sebastian T. Ventrone ,  Keith R. Williams

    IPC分类号： G11C7/00

    CPC分类号： G11C11/417

    摘要： A system for determining a history state of data in a data retaining device are disclosed. A state of a partially-depleted silicon-on-insulator (PD SOI) device coupled to a data retaining device is measured to indicate a body voltage of the PD SOI device. The body voltage of the PD SOI device may indicate, among others, how long the PD SOI device has been idling, which indirectly indicates how long data in the data retaining device has not been accessed. As such, the current invention may be used efficiently with, e.g., a cache replacement algorithm in a management of the data retaining device.

    摘要翻译： 公开了一种用于确定数据保持装置中的数据的历史状态的系统。 耦合到数据保持装置的部分耗尽的绝缘体上硅（PD SOI）器件的状态被测量以指示PD SOI器件的体电压。 PD SOI器件的体电压可以指示PD SOI器件已经空转多长时间，这间接地指示数据保持器件中的数据未被访问多长时间。 因此，本发明可以在数据保留装置的管理中与例如高速缓存替换算法有效地使用。