公开(公告)号：US20180337142A1

公开(公告)日：2018-11-22

申请号：US15980577

申请日：2018-05-15

Applicant: XINTEC INC.

Inventor： Chia-Ming CHENG ,  Po-Han LEE ,  Wei-Chung YANG ,  Kuan-Jung WU ,  Shu-Ming CHANG

IPC: H01L23/00 ,  H01L25/16 ,  H01L27/146 ,  H01L21/56 ,  H01L23/31 ,  H01L23/04

CPC classification number: H01L23/562 ,  H01L21/56 ,  H01L21/561 ,  H01L23/04 ,  H01L23/3107 ,  H01L23/3128 ,  H01L24/09 ,  H01L24/17 ,  H01L25/167 ,  H01L27/14643 ,  H01L2224/02373

Abstract: A chip package is provided. A first bonding structure is disposed on a first redistribution layer (RDL). A first chip includes a sensing region and a conductive pad that are adjacent to an active surface. The first chip is bonded onto the first RDL through the first bonding structure. The first bonding structure is disposed between the conductive pad and the first RDL. A molding layer covers the first RDL and surrounds the first chip. A second RDL is disposed on the molding layer and the first chip and is electrically connected to the first RDL. A second chip is stacked on a non-active surface of the first chip and is electrically connected to the first chip through the second RDL, the first RDL, and the first bonding structure. A method of forming the chip package is also provided.

公开(公告)号：US10109663B2

公开(公告)日：2018-10-23

申请号：US15258594

申请日：2016-09-07

Applicant: XINTEC INC.

Inventor： Yu-Lung Huang ,  Tsang-Yu Liu ,  Yi-Ming Chang ,  Hsin Kuan

IPC: H01L27/146

Abstract: A chip package including a substrate is provided. The substrate has a first surface and a second surface opposite thereto. The substrate includes a sensing region. A cover plate is on the first surface and covers the sensing region. A shielding layer covers a sidewall of the cover plate and extends towards the second surface. The shielding layer has an inner surface adjacent to the cover plate and has an outer surface away from the cover plate. The length of the outer surface extending towards the second surface is less than that of the inner surface extending towards the second surface, and is not less than that of the sidewall of the cover plate. A method of forming the chip package is also provided.

公开(公告)号：US10049252B2

公开(公告)日：2018-08-14

申请号：US14967153

申请日：2015-12-11

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Shu-Ming Chang ,  Tsang-Yu Liu ,  Hsing-Lung Shen

IPC: G06K9/00 ,  H01L21/48 ,  H01L23/498 ,  G06F3/041

Abstract: A chip package includes a substrate, a capacitive sensing layer and a computing chip. The substrate has a first surface and a second surface opposite to the first surface, and the capacitive sensing layer is disposed above the second surface and having a third surface opposite to the second surface, which the capacitive sensing layer includes a plurality of capacitive sensing electrodes and a plurality of metal wires. The capacitive sensing electrodes are on the second surface, and the metal wires are on the capacitive sensing electrodes. The computing chip is disposed above the third surface and electrically connected to the capacitive sensing electrodes.

公开(公告)号：US20180175092A1

公开(公告)日：2018-06-21

申请号：US15895575

申请日：2018-02-13

Applicant: XINTEC INC.

Inventor： Ho-Yin YIU ,  Ying-Nan WEN ,  Chien-Hung LIU ,  Wei-Chung YANG

IPC: H01L27/146

CPC classification number: H01L27/14634 ,  H01L24/19 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1469 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244

Abstract: A chip package is provided. The chip package includes a sensing device. The chip package also includes a first conductive structure disposed on the sensing device and electrically connected to the sensing device. The chip package further includes a chip and a second conductive structure disposed on the sensing device. The chip includes an integrated circuit device. The second conductive structure is positioned on the chip and is electrically connected to the integrated circuit device and the first conductive structure. In addition, the chip package includes an insulating layer covering the sensing device and the chip. The insulating layer has a hole. The first conductive structure is positioned under the bottom of the hole. The top surface of the insulating layer is coplanar with the top surface of the second conductive structure. A method for forming the chip package is also provided.

公开(公告)号：US09997473B2

公开(公告)日：2018-06-12

申请号：US15409289

申请日：2017-01-18

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Tsang-Yu Liu ,  Chia-Sheng Lin ,  Chaung-Lin Lai

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/52 ,  H01L21/54 ,  H01L23/18 ,  H01L23/055 ,  H01L21/48

CPC classification number: H01L23/562 ,  H01L21/4817 ,  H01L21/52 ,  H01L21/54 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/055 ,  H01L23/18 ,  H01L23/3114 ,  H01L23/522 ,  H01L24/16 ,  H01L25/065 ,  H01L27/14618 ,  H01L27/14687 ,  H01L2224/16237

Abstract: A chip package including a substrate is provided. The substrate has a first surface and a second surface opposite thereto. The substrate includes a sensing or device region which is adjacent to the first surface. A recess is in the substrate. The recess extends from the second surface towards the first surface, and vertically overlaps the sensing or device region. A redistribution layer is electrically connected to the sensing or device region, and extends from the second surface into the recess. A method of forming the chip package is also provided.

公开(公告)号：US09859320B2

公开(公告)日：2018-01-02

申请号：US15393006

申请日：2016-12-28

Applicant: XINTEC INC.

Inventor： Shun-Wen Long ,  Guo-Jyun Chiou ,  Meng-Han Kuo ,  Ming-Chieh Huang ,  Hsi-Chien Lin ,  Chin-Kang Chen ,  Yi-Pin Chen

IPC: H01L27/14 ,  H01L27/146

CPC classification number: H01L27/14629 ,  H01L27/14623 ,  H01L27/14636 ,  H01L27/14685 ,  H01L27/14698 ,  H01L2224/11

Abstract: A chip package includes a chip, an insulating layer and a conductive layer. The chip includes a substrate, an epitaxy layer, a device region and a conductive pad. The epitaxy layer is disposed on the substrate, and the device region and the conductive pad are disposed on the epitaxy layer. The conductive pad is at a side of the device region and connected to the device region. The conductive pad protrudes out of a side surface of the epitaxy layer. The insulating layer is disposed below the substrate and extended to cover the side surface of the epitaxy layer. The conductive layer is disposed below the insulating layer and extended to contact the conductive pad. The conductive layer and the side surface of the epitaxy layer are separated by a first distance.

公开(公告)号：US09831185B2

公开(公告)日：2017-11-28

申请号：US15139276

申请日：2016-04-26

Applicant: XINTEC INC.

Inventor： Shih-Yi Lee ,  Ying-Nan Wen ,  Chien-Hung Liu ,  Ho-Yin Yiu

IPC: H01L23/48 ,  H01L23/538 ,  H01L21/78 ,  H01L21/683 ,  H01L23/14 ,  H01L21/48 ,  H01L21/768 ,  H01L23/498

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/145 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2221/68327 ,  H01L2224/13024 ,  H01L2224/18

Abstract: A chip package includes a chip, a laser stop layer, a first through hole, an isolation layer, a second through hole and a conductive layer. The laser stop layer is disposed above a first surface of the chip, and the first through hole is extended from a second surface to the first surface of the chip to expose the laser stop layer. The isolation layer is below the second surface and in the first through hole, and the isolation layer has a third surface opposite to the second surface. The second through hole is extended from the third surface to the first surface, and the second through hole is through the first through hole to expose the laser stop layer. The conductive layer is disposed below the third surface and extended into the second through hole to contact the laser stop layer.

公开(公告)号：US09780050B2

公开(公告)日：2017-10-03

申请号：US15340909

申请日：2016-11-01

Applicant: XINTEC INC.

Inventor： Ying-Nan Wen ,  Chien-Hung Liu ,  Shih-Yi Lee ,  Ho-Yin Yiu

IPC: H01L21/00 ,  H01L23/00 ,  H01L21/76 ,  H01L21/78 ,  H01L21/683 ,  H01L21/268 ,  H01L21/768 ,  H01L21/304 ,  H01L23/498 ,  H01L21/56 ,  H01L23/48 ,  H01L27/146

CPC classification number: H01L24/02 ,  H01L21/268 ,  H01L21/304 ,  H01L21/31127 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76 ,  H01L21/76802 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L27/14678 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/0235 ,  H01L2224/02372 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/03002 ,  H01L2224/0311 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/014

Abstract: A chip package included a chip, a first though hole, a laser stop structure, a first isolation layer, a second though hole and a conductive layer. The first though hole is extended from the second surface to the first surface of the chip to expose a conductive pad, and the laser stop structure is disposed on the conductive pad exposed by the first through hole, which an upper surface of the laser stop structure is above the second surface. The first isolation layer covers the second surface and the laser stop structure, and the first isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the second surface to expose the laser stop structure, and a conductive layer is on the third surface and extended into the second though hole to contact the laser stop structure.

公开(公告)号：US09768067B2

公开(公告)日：2017-09-19

申请号：US15364160

申请日：2016-11-29

Applicant: XINTEC INC.

Inventor： Chien-Hung Liu ,  Ying-Nan Wen ,  Shih-Yi Lee ,  Ho-Yin Yiu

IPC: H01L21/768 ,  H01L21/268 ,  H01L23/48 ,  H01L23/00 ,  H01L23/528 ,  H01L21/683 ,  H01L21/78 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/56 ,  H01L21/263 ,  H01L23/31

CPC classification number: H01L21/76898 ,  H01L21/2633 ,  H01L21/268 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/528 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/43 ,  H01L24/45 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/0233 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06135 ,  H01L2224/06182 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/1411 ,  H01L2224/14181 ,  H01L2224/432 ,  H01L2224/4502 ,  H01L2224/45144 ,  H01L2924/01079 ,  H01L2924/00014

Abstract: A chip package includes a chip, a laser stopper, an isolation layer, a redistribution layer, an insulating layer, and a conductive structure. The chip has a conductive pad, a first surface, and a second surface opposite to the first surface. The conductive pad is located on the first surface. The second surface has a first though hole to expose the conductive pad. The laser stopper is located on the conductive pad. The isolation layer is located on the second surface and in the first though hole. The isolation layer has a third surface opposite to the second surface. The isolation layer and the conductive pad have a second though hole together, such that the laser stopper is exposed through the second though hole. The redistribution layer is located on the third surface, the sidewall of the second though hole, and the laser stopper.

公开(公告)号：US09721911B2

公开(公告)日：2017-08-01

申请号：US14931633

申请日：2015-11-03

Applicant: XINTEC INC.

Inventor： Ho-Yin Yiu ,  Ying-Nan Wen ,  Chien-Hung Liu ,  Shih-Yi Lee

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/683 ,  H01L21/31 ,  H01L21/311 ,  H01L21/78 ,  H01L21/02 ,  G06F21/32 ,  H01L23/525

CPC classification number: H01L24/09 ,  G06F21/32 ,  H01L21/02013 ,  H01L21/31 ,  H01L21/31111 ,  H01L21/6835 ,  H01L21/76831 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/481 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/17 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02311 ,  H01L2224/02372 ,  H01L2224/02381 ,  H01L2224/03002 ,  H01L2224/03462 ,  H01L2224/0391 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/08235 ,  H01L2224/08237 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/03

Abstract: A chip package includes a chip, a laser stopper, an isolation layer, a redistribution layer, an insulating layer, and a conductive structure. The chip has a conductive pad, a first surface, and a second surface. The conductive pad is located on the first surface. The second surface has a first through hole to expose the conductive pad. The laser stopper is located on the conductive pad in the first through hole. The isolation layer is located on the second surface and in the first through hole. The isolation layer has a third surface opposite to the second surface, and has a second through hole to expose the laser stopper. The redistribution layer is located on the third surface, a sidewall of the second through hole, and the laser stopper in the second through hole. The conductive structure is located on the redistribution.