公开(公告)号：US20110214911A1

公开(公告)日：2011-09-08

申请号：US12716271

申请日：2010-03-02

申请人： Seng Guan Chow ,  Heap Hoe Kuan ,  Reza Argenty Pagaila

发明人： Seng Guan Chow ,  Heap Hoe Kuan ,  Reza Argenty Pagaila

IPC分类号： H05K1/16 ,  H05K3/30

CPC分类号： H05K1/16 ,  H01L2224/13028 ,  H05K3/30 ,  Y10T29/4913 ,  Y10T29/49139

摘要： A method of manufacture of a circuit system includes: providing a carrier base; forming a cavity in the carrier base; forming a bridge lead over the cavity, the bridge lead exposing the cavity; and mounting a device having an anchor interconnect, the anchor interconnect is in the cavity and conformal to the bridge lead over the cavity.

摘要翻译： 电路系统的制造方法包括：提供载体基体; 在载体基体中形成空腔; 在空腔上形成桥引线，桥引线暴露空腔; 并且安装具有锚定互连件的装置，所述锚固件互连件在空腔中并且与所述空腔上的所述桥接引线保形。

公开(公告)号：US07989270B2

公开(公告)日：2011-08-02

申请号：US12404134

申请日：2009-03-13

申请人： Rui Huang ,  Heap Hoe Kuan ,  Yaojian Lin ,  Seng Guan Chow

发明人： Rui Huang ,  Heap Hoe Kuan ,  Yaojian Lin ,  Seng Guan Chow

IPC分类号： H01L21/00 ,  H01L21/20

CPC分类号： H01L23/3128 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5389 ,  H01L23/642 ,  H01L24/24 ,  H01L24/48 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2223/6677 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor device is made by forming a plurality of conductive pillars vertically over a temporary carrier. A conformal insulating layer is formed over the conductive pillars. A conformal conductive layer is formed over the conformal insulating layer. A first conductive pillar, conformal insulating layer, and conformal conductive layer constitute a vertically oriented integrated capacitor. A semiconductor die or component is mounted over the carrier. An encapsulant is deposited over the semiconductor die or component and around the conformal conductive layer. A first interconnect structure is formed over a first side of the encapsulant. The first interconnect structure includes an integrated passive device. The first interconnect structure is electrically connected to the semiconductor die or component and vertically oriented integrated capacitor. The carrier is removed. A second interconnect structure is formed over a second side of the encapsulant opposite the first side of the encapsulant.

摘要翻译： 半导体器件通过在临时载体上垂直地形成多个导电柱而制成。 在导电柱上形成保形绝缘层。 在保形绝缘层上形成共形导电层。 第一导电柱，保形绝缘层和共形导电层构成垂直取向的集成电容器。 半导体管芯或部件安装在载体上。 密封剂沉积在半导体管芯或部件上并且在保形导电层周围。 第一互连结构形成在密封剂的第一侧上。 第一互连结构包括集成无源器件。 第一互连结构电连接到半导体管芯或部件和垂直取向的集成电容器。 载体被移除。 第二互连结构形成在与密封剂的第一侧相对的密封剂的第二侧上。

公开(公告)号：US07989269B2

公开(公告)日：2011-08-02

申请号：US12047979

申请日：2008-03-13

申请人： Byung Tai Do ,  Seng Guan Chow ,  Heap Hoe Kuan ,  Linda Pei Ee Chua ,  Rui Huang

发明人： Byung Tai Do ,  Seng Guan Chow ,  Heap Hoe Kuan ,  Linda Pei Ee Chua ,  Rui Huang

IPC分类号： H01L21/00

CPC分类号： H01L21/56 ,  H01L23/3128 ,  H01L24/73 ,  H01L24/97 ,  H01L25/03 ,  H01L25/50 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device is made by mounting a first semiconductor die to a first substrate, forming a first encapsulant over the first semiconductor die, and forming a second encapsulant over the first encapsulant. The second encapsulant is penetrable, thermally conductive material. A second semiconductor die is mounted to the second substrate. A bond wire electrically connects the second semiconductor die to the second substrate. A passive circuit element is mounted to the second substrate. Leading with the second encapsulant, the first substrate is pressed onto the second substrate so that the second encapsulant completely covers the second semiconductor die, bond wire, and passive circuit element. The second encapsulant is then cured. A third encapsulant is formed over the first and second substrates. A shield can be disposed over the second semiconductor die with openings for the second encapsulant to flow through when pressed onto the second substrate.

摘要翻译： 半导体器件通过将第一半导体管芯安装到第一衬底上，在第一半导体管芯上形成第一密封剂，并在第一密封剂上形成第二密封剂。 第二密封剂是可穿透的导热材料。 第二半导体管芯安装到第二衬底。 接合线将第二半导体管芯电连接到第二基板。 无源电路元件安装到第二基板。 利用第二密封剂引导第一衬底被压在第二衬底上，使得第二密封剂完全覆盖第二半导体管芯，接合线和无源电路元件。 然后固化第二密封剂。 在第一和第二基板上形成第三密封剂。 可以在第二半导体管芯上设置屏蔽件，其具有用于第二密封剂的开口，当第二密封剂被压在第二衬底上时流过。

公开(公告)号：US20110180914A1

公开(公告)日：2011-07-28

申请号：US13081011

申请日：2011-04-06

申请人： Byung Tai Do ,  Seng Guan Chow ,  Heap Hoe Kuan ,  Linda Pei Ee Chua ,  Rui Huang

发明人： Byung Tai Do ,  Seng Guan Chow ,  Heap Hoe Kuan ,  Linda Pei Ee Chua ,  Rui Huang

IPC分类号： H01L23/495 ,  H01L21/56

CPC分类号： H01L23/49548 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/4334 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for manufacturing a multiple encapsulation integrated circuit package-in-package system includes: dicing a top integrated circuit wafer having a bottom encapsulant thereon to form a top integrated circuit die with the bottom encapsulant; positioning internal leadfingers adjacent and connected to a bottom integrated circuit die; pressing the bottom encapsulant on to the bottom integrated circuit die; connecting the top integrated circuit die to external leadfingers adjacent the internal leadfingers; and forming a top encapsulant over the top integrated circuit die.

摘要翻译： 一种用于制造多封装集成电路封装包装系统的方法，包括：在其上划分具有底部密封剂的顶部集成电路晶片，以形成具有底部密封剂的顶部集成电路裸片; 将内部引线定位在相邻并连接到底部集成电路管芯上; 将底部密封剂压在底部集成电路模具上; 将顶部集成电路管芯连接到与内部引线管相邻的外部引线管; 以及在顶部集成电路管芯上形成顶部密封剂。

公开(公告)号：US07986032B2

公开(公告)日：2011-07-26

申请号：US12547439

申请日：2009-08-25

申请人： Seng Guan Chow ,  Ming Ying ,  Ii Kwon Shim ,  Lip Seng Tan

发明人： Seng Guan Chow ,  Ming Ying ,  Ii Kwon Shim ,  Lip Seng Tan

IPC分类号： H01L23/495

CPC分类号： H01L23/3107 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/49109 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/4943 ,  H01L2224/73265 ,  H01L2224/85207 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package system is provided. A substrate having a die attach paddle is provided. A first plurality of leads is provided around the die attach paddle having a first plurality of lead tips. A second plurality of leads is provided around the die attach paddle interleaved with the first plurality of leads, at least some of the second plurality of leads having a plurality of depression lead tips. A first die is attached to the die attach paddle. The die is wire bonded to the first plurality of leads and the second plurality of leads. The die is encapsulated.

摘要翻译： 提供半导体封装系统。 提供具有管芯附接板的衬底。 第一组多个引线设置在具有第一多个引线端的管芯附接焊盘的周围。 第二多个引线设置在与第一多个引线交错的管芯附接焊盘周围，第二多个引线中的至少一些具有多个凹陷引线尖端。 第一管芯附接到管芯附接板上。 模具被引线接合到第一多个引线和第二多个引线。 模具被封装。

公开(公告)号：US07981702B2

公开(公告)日：2011-07-19

申请号：US11276647

申请日：2006-03-08

申请人： Tsz Yin Ho ,  Dioscoro A. Merilo ,  Seng Guan Chow ,  Antonio B. Dimaano, Jr. ,  Heap Hoe Kuan

发明人： Tsz Yin Ho ,  Dioscoro A. Merilo ,  Seng Guan Chow ,  Antonio B. Dimaano, Jr. ,  Heap Hoe Kuan

IPC分类号： G01R31/26 ,  H01L21/66 ,  H01L21/00

CPC分类号： H01L25/105 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： An integrated circuit package in package system including forming a base integrated circuit package with a base lead having a portion with a substantially planar base surface, forming an extended-lead integrated circuit package with an extended lead having a portion with a substantially planar lead-end surface, and stacking the extended-lead integrated circuit package over the base integrated circuit package with the substantially planar lead-end surface coplanar with the substantially planar base surface.

摘要翻译： 一种封装系统中的集成电路封装，包括形成具有基部引线的基极集成电路封装，所述基极引线具有基本平坦的基面的部分，形成具有延伸引线的延伸引线集成电路封装，所述延伸引线具有基本平坦的引线端 表面，并且在基本集成电路封装上堆叠延伸引线集成电路封装，其中基本平坦的引出端表面与基本平坦的基面共面。

公开(公告)号：US20110079899A1

公开(公告)日：2011-04-07

申请号：US12964638

申请日：2010-12-09

申请人： You Yang Ong ,  Dioscoro A. Merilo ,  Seng Guan Chow

发明人： You Yang Ong ,  Dioscoro A. Merilo ,  Seng Guan Chow

IPC分类号： H01L23/48 ,  H01L21/56

CPC分类号： H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/97 ,  H01L25/16 ,  H01L2223/54433 ,  H01L2223/54473 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/18162 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/0206 ,  H05K1/185 ,  H05K3/4602

摘要： A method of manufacture of an embedded integrated circuit package system includes: forming a first conductive pattern on a first structure; connecting a first integrated circuit die, having bumps on a first active side, directly on the first conductive pattern by the bumps; forming a substrate forming encapsulation to cover the first integrated circuit die and the first conductive pattern; forming a channel in the substrate forming encapsulation; and applying a conductive material in the channel.

摘要翻译： 嵌入式集成电路封装系统的制造方法包括：在第一结构上形成第一导电图案; 通过所述凸块直接在所述第一导电图案上连接具有第一有源侧上的凸块的第一集成电路裸片; 形成衬底形成封装以覆盖第一集成电路管芯和第一导电图案; 在衬底形成封装中形成通道; 以及在所述通道中施加导电材料。

公开(公告)号：US07863726B2

公开(公告)日：2011-01-04

申请号：US12612630

申请日：2009-11-04

申请人： Seng Guan Chow ,  Tae Hoan Jang

发明人： Seng Guan Chow ,  Tae Hoan Jang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L23/02 ,  H01L29/40 ,  H01L23/28 ,  H01L23/29 ,  H01L23/544 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L23/49816 ,  H01L23/3128 ,  H01L23/544 ,  H01L24/48 ,  H01L24/73 ,  H01L2223/54433 ,  H01L2223/54473 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/3436 ,  H05K3/3442 ,  H05K2201/094 ,  H05K2201/09781 ,  Y02P70/613 ,  Y10S438/975 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacture of an integrated circuit package system includes: forming a package substrate with a top substrate side and a bottom substrate side; forming a corner contact in a first corner of the bottom substrate side, the corner contact extending to a substrate edge of the package substrate; mounting an integrated circuit device over the top substrate side; connecting an electrical interconnect between the integrated circuit device and the top substrate side; and forming a package encapsulation over the top substrate side, the integrated circuit device, and the electrical interconnect.

摘要翻译： 一种集成电路封装系统的制造方法，包括：形成具有顶部衬底侧和底部衬底侧的封装衬底; 在所述底部基板侧的第一角部中形成角接触，所述角接触部延伸到所述封装基板的基板边缘; 在顶部基板侧上安装集成电路器件; 连接集成电路器件和顶部衬底侧之间的电气互连; 以及在顶部衬底侧，集成电路器件和电互连件上形成封装封装。

公开(公告)号：US07859098B2

公开(公告)日：2010-12-28

申请号：US11379332

申请日：2006-04-19

申请人： You Yang Ong ,  Dioscoro A. Merilo ,  Seng Guan Chow

发明人： You Yang Ong ,  Dioscoro A. Merilo ,  Seng Guan Chow

IPC分类号： H01L23/04

CPC分类号： H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/97 ,  H01L25/16 ,  H01L2223/54433 ,  H01L2223/54473 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/18162 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/0206 ,  H05K1/185 ,  H05K3/4602

摘要： An embedded integrated circuit package system is provided forming a first conductive pattern on a first structure, connecting a first integrated circuit die on the first conductive pattern, forming a substrate forming encapsulation to cover the first integrated circuit die and the first conductive pattern, forming a channel in the substrate forming encapsulation, and applying a conductive material in the channel.

摘要翻译： 提供了一种在第一结构上形成第一导电图案的嵌入式集成电路封装系统，将第一集成电路管芯连接在第一导电图案上，形成衬底形成封装以覆盖第一集成电路管芯和第一导电图案，形成 在衬底形成封装中的通道，以及在沟道中施加导电材料。

公开(公告)号：US07838899B2

公开(公告)日：2010-11-23

申请号：US12623351

申请日：2009-11-20

申请人： Seng Guan Chow ,  Heap Hoe Kuan

发明人： Seng Guan Chow ,  Heap Hoe Kuan

IPC分类号： H01L29/24 ,  H01L31/0203

CPC分类号： H01L27/14618 ,  H01L2224/48227 ,  H01L2924/01067 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/10156 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012

摘要： An integrated circuit package system is provided including providing a wafer including image sensor systems having interconnects connected thereto and encapsulating the image sensor systems and interconnects in a transparent encapsulant. The system includes removing a portion of the transparent encapsulant to expose portions of the interconnects and singulating the wafer to form image sensor devices including at least one of the image sensor systems and a number of the interconnects.