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    MEMORY SYSTEM WITH THREADED TRANSACTION SUPPORT
    163.
    发明公开
    MEMORY SYSTEM WITH THREADED TRANSACTION SUPPORT 审中-公开

    公开(公告)号：US20240111423A1

    公开(公告)日：2024-04-04

    申请号：US18492296

    申请日：2023-10-23

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Ely Tsern

    IPC: G06F3/06 ,  G06F12/06 ,  G11C5/04 ,  G11C7/10

    CPC classification number: G06F3/0611 ,  G06F3/0619 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0607 ,  G11C5/04 ,  G11C7/10

    Abstract: Memory modules, systems, memory controllers and associated methods are disclosed. In one embodiment, a memory module includes a module substrate having first and second memory devices. Buffer circuitry disposed on the substrate couples to the first and second memory devices via respective first and second secondary interfaces. The buffer circuitry includes a primary signaling interface for coupling to a group of signaling links associated with a memory controller. The primary signaling interface operates at a primary signaling rate and the first and second secondary data interfaces operate at a secondary signaling rate. During a first mode of operation, the primary interface signaling rate is at least twice the secondary signaling rate. A first time interval associated with a transfer of first column data via the first secondary interface temporally overlaps a second time interval involving second column data transferred via the second secondary interface.

    DETERMINISTIC OPERATION OF STORAGE CLASS MEMORY
    164.
    发明公开
    DETERMINISTIC OPERATION OF STORAGE CLASS MEMORY 审中-公开

    公开(公告)号：US20240054084A1

    公开(公告)日：2024-02-15

    申请号：US18239681

    申请日：2023-08-29

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Brent Haukness

    IPC: G06F13/16

    CPC classification number: G06F13/1689

    Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory controller is disclosed. The memory controller includes write queue logic that has first storage to temporarily store signal components of a write operation. The signal components include an address and write data. A transfer interface issues the signal components of the write operation to a bank of a storage class memory (SCM) device and generates a time value. The time value represents a minimum time interval after which a subsequent write operation can be issued to the bank. The write queue logic includes an issue queue to store the address and the time value for a duration corresponding to the time value.

    Nonvolatile Physical Memory with DRAM Cache
    169.
    发明公开
    Nonvolatile Physical Memory with DRAM Cache 审中-公开

    公开(公告)号：US20230359559A1

    公开(公告)日：2023-11-09

    申请号：US18203569

    申请日：2023-05-30

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Christopher Haywood

    IPC: G06F12/0804 ,  G06F12/12

    CPC classification number: G06F12/0804 ,  G06F12/12 ,  G06F2212/1044 ,  G06F2212/205 ,  G11C14/0018

    Abstract: A hybrid volatile/non-volatile memory module employs a relatively fast, durable, and expensive dynamic, random-access memory (DRAM) cache to store a subset of data from a larger amount of relatively slow and inexpensive nonvolatile memory (NVM). A module controller prioritizes accesses to the DRAM cache for improved speed performance and to minimize programming cycles to the NVM. Data is first written to the DRAM cache where it can be accessed (written to and read from) without the aid of the NVM. Data is only written to the NVM when that data is evicted from the DRAM cache to make room for additional data. Mapping tables relating NVM addresses to physical addresses are distributed throughout the DRAM cache using cache line bits that are not used for data.

    Strobe acquisition and tracking
    170.
    发明授权
    Strobe acquisition and tracking 有权

    公开(公告)号：US11790962B2

    公开(公告)日：2023-10-17

    申请号：US17305654

    申请日：2021-07-12

    Applicant: Rambus Inc.

    Inventor： Bret Stott ,  Frederick A. Ware ,  Ian P. Shaeffer ,  Yuanlong Wang

    IPC: G11C7/22 ,  G06F13/16 ,  G11C7/02

    CPC classification number: G11C7/222 ,  G06F13/1689 ,  G11C7/02 ,  G11C7/22

    Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.

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