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    Methods for forming porous insulator structures on semiconductor devices
    172.
    发明申请
    Methods for forming porous insulator structures on semiconductor devices 有权
    在半导体器件上形成多孔绝缘体结构的方法

    公开(公告)号：US20050032395A1

    公开(公告)日：2005-02-10

    申请号：US10933061

    申请日：2004-09-01

    Applicant: Warren Farnworth ,  Tongbi Jiang

    Inventor： Warren Farnworth ,  Tongbi Jiang

    IPC: H01L21/316 ,  H01L21/768 ,  H01L23/532 ,  H01L21/469

    CPC classification number: H01L21/02203 ,  H01L21/02126 ,  H01L21/02282 ,  H01L21/02345 ,  H01L21/02354 ,  H01L21/31695 ,  H01L21/7682 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/00

    Abstract: A method for forming a porous insulative structure on a semiconductor device structure includes forming a layer of unconsolidated electrically insulative, or dielectric, material with microcapsules dispersed therethrough on at least a portion of the surface of the semiconductor device structure. The microcapsules may be hollow or include a removable filler. Once the layer has been formed, the unconsolidated material is at least partially consolidated. Filler, if any, may be removed from the microcapsules to provide a porous insulative layer or structure. This layer or structure may be configured to support conductive elements or other features of the semiconductor device.

    Abstract translation: 在半导体器件结构上形成多孔绝缘结构的方法包括在半导体器件结构的表面的至少一部分上形成分散在其中的微胶囊的未固结的电绝缘或介电材料层。 微胶囊可以是中空的或包括可除去的填料。 一旦形成了该层，则未合并的材料至少部分地被固结。 填充物（如果有的话）可以从微胶囊中除去以提供多孔绝缘层或结构。 该层或结构可以被配置为支撑半导体器件的导电元件或其它特征。

    Method for in-line testing of flip-chip semiconductor assemblies
    174.
    发明申请
    Method for in-line testing of flip-chip semiconductor assemblies 失效

    公开(公告)号：US20050024080A1

    公开(公告)日：2005-02-03

    申请号：US10927546

    申请日：2004-08-25

    Applicant: Chad Cobbley ,  John VanNortwick ,  Bret Street ,  Tongbi Jiang

    Inventor： Chad Cobbley ,  John VanNortwick ,  Bret Street ,  Tongbi Jiang

    IPC: G01R1/04 ,  G01R31/26

    CPC classification number: G01R1/0483 ,  Y10T29/4913 ,  Y10T29/49144

    Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

    Method for in-line testing of flip-chip semiconductor assemblies
    175.
    发明申请
    Method for in-line testing of flip-chip semiconductor assemblies 失效

    公开(公告)号：US20050007141A1

    公开(公告)日：2005-01-13

    申请号：US10900609

    申请日：2004-07-27

    Applicant: Chad Cobbley ,  John VanNortwick ,  Bret Street ,  Tongbi Jiang

    Inventor： Chad Cobbley ,  John VanNortwick ,  Bret Street ,  Tongbi Jiang

    IPC: G01R1/04 ,  G01R31/26

    CPC classification number: G01R1/0483 ,  Y10T29/4913 ,  Y10T29/49144

    Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

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