公开(公告)号：US20050176272A1

公开(公告)日：2005-08-11

申请号：US10787647

申请日：2004-02-05

Applicant: Steven Rosenau

Inventor： Steven Rosenau

IPC: H01R12/00 ,  H05K1/00 ,  H05K1/02 ,  H05K1/11 ,  H05K1/14 ,  H05K3/34 ,  H05K7/02 ,  H05K7/06 ,  H05K7/08 ,  H05K7/10

CPC classification number: H05K1/112 ,  H05K1/0237 ,  H05K1/0298 ,  H05K3/3421 ,  H05K3/3436 ,  H05K2201/09472 ,  H05K2201/10704 ,  H05K2201/10734 ,  H05K2203/049

Abstract: An electrical component, such as a trace, signal line, or contact pad connected to the trace or signal line, is covered by one or more layers. The electrical component is connected directly to an electrical device by forming an opening through the one or more layers. The opening exposes a portion of the electrical component. A connector, such as a solder ball, a pin contact, or a wire bond, is then attached to the exposed portion of the electrical component. The connector connects directly to another electrical device to create an electrical connection between the electrical component and the electrical device. The electrical device may be configured, for example, as a second signal line or contact pad in another stripline circuit, a microstrip circuit, an integrated circuit, or an electrical component.

Abstract translation: 连接到迹线或信号线的电气部件，例如迹线，信号线或接触焊盘，被一层或多层覆盖。 电气部件通过形成通过一个或多个层的开口直接连接到电气装置。 开口露出电气部件的一部分。 然后将诸如焊球，针接触或引线接合的连接器附接到电气部件的暴露部分。 连接器直接连接到另一个电气设备，以在电气部件和电气设备之间形成电连接。 电气设备可以被配置为例如另一个带状线电路中的第二信号线或接触焊盘，微带电路，集成电路或电气部件。

公开(公告)号：US06884707B1

公开(公告)日：2005-04-26

申请号：US10075060

申请日：2002-02-11

Applicant: Gabe Cherian

Inventor： Gabe Cherian

IPC: H01L23/495 ,  H01L23/498 ,  H05K3/34 ,  H01L21/44

CPC classification number: H01L24/12 ,  H01L23/49555 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/97 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K3/3426 ,  H05K2201/09418 ,  H05K2201/10318 ,  H05K2201/10386 ,  H05K2201/10689 ,  H05K2201/10704 ,  H05K2201/10825 ,  Y02P70/613 ,  H01L2224/29099 ,  H01L2924/00

Abstract: The present invention relates generally to permanent interconnections between electronic devices, such as integrated circuit packages, chips, wafers and printed circuit boards or substrates, or similar electronic devices. More particularly it relates to high-density electronic devices.The invention describes means and methods that can be used to counteract the undesirable effects of thermal cycling, shock and vibrations and severe environment conditions in general.For leaded devices, the leads are oriented to face the thermal center of the devices and the system they interact with.For leadless devices, the mounting elements are treated or prepared to control the migration of solder along the length of the elements, to ensure that those elements retain their desired flexibility.

Abstract translation: 本发明一般涉及电子设备之间的永久互连，例如集成电路封装，芯片，晶片和印刷电路板或基板或类似的电子设备。 更具体地说，涉及高密度电子设备。 本发明描述了可用于抵消热循环，冲击和振动以及恶劣环境条件的不良影响的手段和方法。 对于有铅器件，引线面向设备的热中心及其与之相互作用的系统。 对于无引线器件，安装元件被处理或准备好以控制沿着元件长度的焊料的迁移，以确保这些元件保持其期望的柔性。

公开(公告)号：US06830177B2

公开(公告)日：2004-12-14

申请号：US10238118

申请日：2002-09-10

Applicant: Deepak K. Pai

Inventor： Deepak K. Pai

IPC: B23K3102

CPC classification number: H01L23/49827 ,  H01L2224/16 ,  H05K3/3421 ,  H05K3/3484 ,  H05K2201/10424 ,  H05K2201/10704 ,  H05K2201/10719 ,  Y02P70/613

Abstract: The present invention comprises cost-effectively manufactured, electrically conductive and mechanically compliant micro-leads and a method of utilizing these compliant micro-leads to interconnect area grid array chip scale packages (“CSPs”) to printed wiring boards (“PWBs”). The preferred method includes orienting a plurality of conductive compliant micro-leads, secured to one another in parallel with tie bars and tooling, to align with a corresponding pattern of conductive pads located along the surface of an area grid array CSP. The compliant micro-leads are electrically connected and mechanically secured to the corresponding connecting surfaces of the area grid array CSP. Next, the securing tie bars and the tooling are removed. The opposite ends of the conductive compliant micro-leads are then oriented to align with a corresponding pattern of conductive surface pads on a PWB. The opposite end of each compliant micro-lead is then electrically connected and mechanically secured to its corresponding connecting pad located on the surface of the PWB, thereby establishing a compliant electrical connection between the area grid array CSP and the PWB. An alternative embodiment of the present invention utilizes an area grid array interposer with compliant micro-leads to provide additional compliancy.

Abstract translation: 本发明包括成本有效的制造，导电和机械兼容的微引线以及利用这些柔性微引线将区域格栅阵列芯片级封装（“CSP”）互连到印刷电路板（“PWB”）的方法。 优选的方法包括使多个导电柔性微引线定向成与导杆和工具平行地彼此固定，以与沿着区域栅格阵列CSP的表面定位的导电焊盘的对应图案对准。 柔性微引线电连接并机械固定到区域网格阵列CSP的对应连接表面。 接下来，拆下固定连接杆和工具。 然后将导电顺应性微引线的相对端定向成与P​​WB上的导电表面焊盘的相应图案对准。 然后，每个柔性微引线的相对端电连接并机械固定到位于PWB表面上的相应的连接焊盘，从而在区域栅格阵列CSP和PWB之间建立顺从的电连接。 本发明的替代实施例利用具有柔性微引线的区域栅格阵列插入器来提供额外的符合性。

公开(公告)号：US06800545B2

公开(公告)日：2004-10-05

申请号：US10261727

申请日：2002-10-01

Applicant: Stuart D. Downes

Inventor： Stuart D. Downes

IPC: H01L2144

CPC classification number: H01R12/585 ,  H01R43/0256 ,  H05K3/3447 ,  H05K3/3452 ,  H05K13/04 ,  H05K2201/10704 ,  H05K2201/10818 ,  H05K2201/10856 ,  H05K2201/10984 ,  H05K2203/0415 ,  H05K2203/0557

Abstract: The invention is directed to techniques for forming a soldered connection using a pin having a channel. The channel enables the pin to form a secure connection with a via (e.g., by facilitating gas percolation out of the via hole during soldering to improve solder flow, by holding solder prior to pin insertion and soldering, or by facilitating accurate pin bending to hold solder or a pin insert prior to pin insertion and soldering) to improve connection system reliability and increase manufacturing yields. In one arrangement, the pin has a surface which includes (i) a first surface area, (ii) a second surface area that is substantially parallel to the first surface area, and (iii) a channel surface area which defines a channel that extends from the first surface area toward the second surface area. To form a soldered connection, the pin is inserted into a cavity defined by a via of a connecting member (e.g., a circuit board), in a direction that is parallel to a central axis of the via. The pin is then soldered to the via to establish an electrical pathway between the pin and the via. Depending on the particular arrangement, the channel generally facilitates the introduction of solder into the cavity of the via. Accordingly, the cavity dimension of the via can be smaller than that required for vias of a conventional reflow soldering approach (i.e., less than 100% of the maximum pin cross-section as for a conventional reflow soldering approach). Hence, the invention is suitable for use in high-density, micro-soldered connection arrangements (e.g., in situations with vias closer together than in the conventional reflow soldering approach).

Abstract translation: 本发明涉及使用具有通道的销形成焊接连接​​的技术。 该通道使引脚与通孔形成牢固的连接（例如，通过在焊接期间促进气体渗透出通孔，以改善焊料流动，通过在引脚插入和焊接之前保持焊料，或通过促进精确的引脚弯曲来保持 焊接或插针插入，然后插入和焊接），以提高连接系统的可靠性并提高制造产量。 在一种布置中，销具有表面，其包括（i）第一表面区域，（ii）基本上平行于第一表面区域的第二表面区域，以及（iii）限定延伸的通道的通道表面区域 从第一表面区域朝向第二表面区域。 为了形成焊接连接​​，销在与通孔的中心轴平行的方向插入到由连接构件（例如电路板）的通孔限定的空腔中。 然后将引脚焊接到通孔，以在引脚和通孔之间建立电路径。 根据具体的布置，通道通常有助于将焊料引入到通孔的空腔中。 因此，通孔的腔体尺寸可以小于常规回流焊接方法的通孔所需的腔体尺寸（即，对于传统的回流焊接方法，其小于最大引脚横截面的100％）。 因此，本发明适用于高密度，微焊接的连接装置（例如，在通孔比常规回流焊接方法更靠近的情况下）。

公开(公告)号：US20040068867A1

公开(公告)日：2004-04-15

申请号：US10272075

申请日：2002-10-15

Inventor： Edward Allyn Burton

IPC: H05K003/30

CPC classification number: H05K1/141 ,  H05K1/0231 ,  H05K1/182 ,  H05K2201/049 ,  H05K2201/09072 ,  H05K2201/10378 ,  H05K2201/1053 ,  H05K2201/10704 ,  H05K2201/10727 ,  Y10T29/4913 ,  Y10T29/49169

Abstract: A method and apparatus is presented to allow one or more electrical components to be coupled to the land-side of an integrated circuit package coupled to a circuit board. In a first embodiment, a void is provided in the circuit board, and a peripheral area of the integrated circuit package is coupled to a peripheral area around the void. This provides space for the insertion of components in the land-side of the integrated circuit package. In a second embodiment, a spacer is provided coupled to the peripheral area of the integrated circuit package to allow the insertion of components into the land-side of the package and above the circuit board. With these embodiments of the present invention, components, such as decoupling capacitors can be coupled closer to the die (e.g., a processor die) of the package thus reducing parasitic inductance.

Abstract translation: 提出了一种方法和装置，以允许一个或多个电气部件耦合到耦合到电路板的集成电路封装的焊盘侧。 在第一实施例中，在电路板中提供空隙，并且集成电路封装的周边区域耦合到空隙周围的周边区域。 这提供了用于在集成电路封装的陆侧插入部件的空间。 在第二实施例中，提供连接到集成电路封装的周边区域的间隔件，以允许将部件插入封装的焊盘侧并且在电路板上方。 利用本发明的这些实施例，诸如去耦电容器的组件可以更靠近封装的管芯（例如，处理器管芯）耦合，从而减小寄生电感。

公开(公告)号：US20040061241A1

公开(公告)日：2004-04-01

申请号：US10261544

申请日：2002-09-30

Inventor： Edward P. Osburn ,  Erik W. Peter ,  Timothy M. Gates

IPC: H01L023/48 ,  H01L021/44

CPC classification number: H05K1/0262 ,  H01L23/49838 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/0219 ,  H05K1/0231 ,  H05K1/0263 ,  H05K1/112 ,  H05K3/429 ,  H05K2201/093 ,  H05K2201/1003 ,  H05K2201/10515 ,  H05K2201/10545 ,  H05K2201/10704 ,  H05K2201/10734 ,  H01L2924/00

Abstract: A method and an apparatus for improving the delivery and filtering of power to a semiconductor device is disclosed by organizing out interconnects (pins, balls, pads or other interconnects) used to carry power in a striped configuration that shortens the conductive path required between a power source and a semiconductor device and that reduces the resistance of that conductive path.

公开(公告)号：US20040041002A1

公开(公告)日：2004-03-04

申请号：US10656559

申请日：2003-09-05

Applicant: Intel Corporation

Inventor： Cheryl M. Waldron-Floyde ,  Brad C. Irwin

IPC: B23K037/00

CPC classification number: H05K13/0465 ,  H05K3/303 ,  H05K2201/10318 ,  H05K2201/10424 ,  H05K2201/10704 ,  H05K2203/0278 ,  H05K2203/167 ,  Y02P70/613 ,  Y10T29/49149 ,  Y10T29/53978

Abstract: An alignment weight is provided. The alignment weight includes a body of material having first and second opposing surfaces. A number of depressions are formed in the first surface. The depressions receive pins of a floating pin field when placed on a floating pin field during connection of the floating pin field to a printed circuit board.

Abstract translation: 提供了对准重量。 对准重量包括具有第一和第二相对表面的材料体。 在第一表面形成多个凹陷。 当将浮动引脚字段连接到印刷电路板时，凹陷接收浮置引脚的引脚。

公开(公告)号：US06663440B2

公开(公告)日：2003-12-16

申请号：US10194170

申请日：2002-07-12

Applicant: Allen Ronald Cox ,  Stephen Peter Legg ,  Neil Morris

Inventor： Allen Ronald Cox ,  Stephen Peter Legg ,  Neil Morris

IPC: H01R1324

CPC classification number: G11B33/121 ,  H01R12/523 ,  H01R12/721 ,  H05K1/112 ,  H05K2201/09472 ,  H05K2201/09845 ,  H05K2201/10189 ,  H05K2201/10704

Abstract: This invention relates to apparatus and a method for connecting a pin array and a circuit board. In particular, the invention relates to pin array connections used in connecting disk drives into disk drive enclosures. Connection is accomplished by using a multi-pinned plug connector which sequentially engages conductive surfaces at different levels within the receiving PCB. The plug connector is connected electrically at its opposing end to a second PCB.

Abstract translation: 本发明涉及一种用于连接针阵列和电路板的装置和方法。 特别地，本发明涉及用于将磁盘驱动器连接到磁盘驱动器机箱中的引脚阵列连接。 通过使用多针式插头连接器实现连接，该插头连接器顺序地接合在接收PCB内的不同级别的导电表面。 插头连接器在其相对端处电连接到第二PCB。

公开(公告)号：US06638080B2

公开(公告)日：2003-10-28

申请号：US09764551

申请日：2001-01-18

Applicant: Kenneth W Johnson ,  Brent A. Holcombe

Inventor： Kenneth W Johnson ,  Brent A. Holcombe

IPC: G01R3102

CPC classification number: H05K3/3447 ,  G01R1/0483 ,  H05K1/189 ,  H05K2201/10325 ,  H05K2201/10704 ,  H05K2203/0415

Abstract: An integrated probe assembly provides the capability to test integrated circuit (IC) packages mounted onto ball grid arrays. The present invention comprises an unsealed BGA socket (102), nail head pins (107) which can be inserted flush into a pin carrier to produce a PGA header (103), a Flex circuit assembly comprising a piece of flexible circuit (104) with various passive resistors and connectors attached and solder preforms (113) used to solder the flex assembly to the pin grid array. Matched impedance connectors (105) are attached at an end of the flexible circuit.

Abstract translation: 集成探头组件提供测试安装在球栅阵列上的集成电路（IC）封装的能力。 本发明包括一个未密封的BGA插座（102），钉头销（107），可以插入针脚托架中以形成PGA插头（103），Flex电路组件包括一片柔性电路（104） 各种被动电阻器和连接器和用于将柔性组件焊接到针栅阵列的焊料预成型件（113）。 匹配阻抗连接器（105）附接在柔性电路的一端。

公开(公告)号：US20030176013A1

公开(公告)日：2003-09-18

申请号：US10063036

申请日：2002-03-13

Applicant: GlobespanVirata Incorporated

Inventor： David Stuart Baker

IPC: H01L021/44 ,  H01L023/48

CPC classification number: H05K3/303 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/0268 ,  H05K1/029 ,  H05K1/0295 ,  H05K3/306 ,  H05K2201/09954 ,  H05K2201/10704 ,  H05K2201/10734 ,  H05K2203/163 ,  Y02P70/613 ,  Y10T29/49139 ,  Y10T29/49169 ,  Y10T29/49208 ,  H01L2924/00

Abstract: An integrated circuit design is provided capable of operating in multiple insertion orientations. In particular, the inventive circuit design includes an integrated circuit package having a plurality of contact elements extending from the integrated circuit package and arranged symmetrically thereon for enabling the integrated circuit to be inserted on a circuit board in at least two discrete orientations. A plurality of the contact elements are designated as orientation pins, the orientation pins being arranged such that, upon integrated circuit package power up, the orientation pins transmit orientation signals indicative of the integrated circuit packages insertion orientation in the circuit board. A plurality of multiplexer devices are provided for routing signals between the contact elements and integrated circuit functional circuitry in response to the orientation signals from the orientation pins.

Abstract translation: 提供能够以多个插入方向操作的集成电路设计。 具体地，本发明的电路设计包括集成电路封装，其具有从集成电路封装延伸并且对称地布置的多个接触元件，以使集成电路能够以至少两个离散取向插入电路板上。 多个接触元件被指定为定位销，所述定向销布置成使得在集成电路封装上电时，定向销将指示集成电路封装在电路板中的插入取向的取向信号传送。 提供多个多路复用器装置用于响应于来自定向销的取向信号在接触元件和集成电路功能电路之间路由信号。