公开(公告)号：US09653452B2

公开(公告)日：2017-05-16

申请号：US15174236

申请日：2016-06-06

Applicant: SOCIONEXT INC.

Inventor： Shiro Usami

IPC: H01L23/52 ,  H01L27/02 ,  H01L29/861 ,  H01L23/528

CPC classification number: H01L27/0292 ,  H01L23/528 ,  H01L23/5286 ,  H01L27/0248 ,  H01L27/0251 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/0262 ,  H01L27/0266 ,  H01L27/0288 ,  H01L29/861 ,  H01L29/87

Abstract: Diffusion regions having the same conductivity type are arranged on a side of a second wiring and a side of a third wiring, respectively under a first wiring connected to a signal terminal. Diffusion regions are separated in a whole part or one part of a range in a Y direction. That is, under first wiring, diffusion regions are only formed in parts opposed to diffusion regions formed under the second wiring and third wiring connected to a power supply terminal or a ground terminal, and a diffusion region is not formed in a central part in an X direction. Therefore, terminal capacity of the signal terminal can be reduced without causing ESD resistance to be reduced, in an ESD protection circuit with the signal terminal.

公开(公告)号：US09652635B2

公开(公告)日：2017-05-16

申请号：US14091475

申请日：2013-11-27

Applicant: Socionext Inc.

Inventor： Seiji Goto ,  Jun Kamada ,  Taiji Tamiya

IPC: G06F12/14 ,  G06F11/30 ,  G06F21/70 ,  G06F21/52 ,  G06F21/55 ,  G06F21/57 ,  G06F21/64 ,  G06F21/71 ,  G06F21/72

CPC classification number: G06F21/70 ,  G06F12/1027 ,  G06F12/1408 ,  G06F13/24 ,  G06F21/52 ,  G06F21/53 ,  G06F21/554 ,  G06F21/575 ,  G06F21/64 ,  G06F21/71 ,  G06F21/72 ,  G06F21/74 ,  G06F2212/1052 ,  G06F2212/682

Abstract: The instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform an encryption processing for the input and output data between the core and the outside.

公开(公告)号：US20170117268A1

公开(公告)日：2017-04-27

申请号：US15402952

申请日：2017-01-10

Applicant: SOCIONEXT INC.

Inventor： Koichi TANIGUCHI ,  Masato MAEDE

IPC: H01L27/02 ,  H01L29/06 ,  H01L27/092 ,  H01L23/50 ,  H01L23/528

CPC classification number: H01L27/0292 ,  H01L23/50 ,  H01L23/528 ,  H01L23/544 ,  H01L27/0207 ,  H01L27/0928 ,  H01L29/0619 ,  H01L29/0623 ,  H01L2924/0002 ,  H03K3/354 ,  H01L2924/00

Abstract: In a semiconductor integrated circuit device, a plurality of electrode pads for external connection are arranged in a zigzag pattern. Some electrode pads of the electrode pads of the plurality of I/O cells which are closer to a side of the semiconductor chip, each have an end portion closer to the side of the semiconductor chip, the end portion being set at the same position as that of an end portion of the corresponding I/O cell. A power source-side protective circuit and a ground-side protective circuit against discharge of static electricity are provided with the power source-side protective circuit being closer to the scribe region. A distance between a center position of one of the electrode pads and the ground-side protective circuit of the corresponding I/O cell and a distance between a center position of the other one electrode pad and the ground-side protective circuit of the corresponding I/O cell are both short and are substantially equal between each I/O cell.

公开(公告)号：US09628076B2

公开(公告)日：2017-04-18

申请号：US15136374

申请日：2016-04-22

Applicant: Socionext Inc.

Inventor： Nobumasa Hasegawa

IPC: H03K3/00 ,  H03K17/687 ,  H03K19/0175 ,  H01L23/66 ,  H03F3/45 ,  H03M9/00 ,  H04L25/00 ,  H03F3/217

CPC classification number: H03K17/687 ,  H01L23/66 ,  H01L2223/6638 ,  H01L2223/665 ,  H01L2223/6655 ,  H03F3/2173 ,  H03F3/45071 ,  H03F3/45179 ,  H03F2200/453 ,  H03F2203/45026 ,  H03K19/0175 ,  H03K19/017545 ,  H03M9/00 ,  H04L25/00 ,  H04L25/0272 ,  H04L25/0278

Abstract: A transmission circuit includes a driver circuit that includes: a transistor to regulate output impedance, and a switching circuit that is connected to the transistor to regulate output impedance and switches an output polarity for differential output; and a bias circuit that includes: a first replica circuit including another transistor corresponding to the transistor to regulate output impedance, the bias circuit generating a gate voltage so as to make a current-voltage characteristic of the transistor to regulate output impedance correspond to a first output impedance value, and supply the gate voltage to a gate of the transistor to regulate output impedance.

公开(公告)号：US09570131B2

公开(公告)日：2017-02-14

申请号：US15262562

申请日：2016-09-12

Applicant: Socionext Inc.

Inventor： Yoshihiro Kishimoto ,  Yoichiro Miki ,  Yuji Sekiguchi

IPC: G11C7/00 ,  G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22

Abstract: A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A strobe latch section produces check data in synchronism with each of the delayed strobe signals, and a system latch section latches, with a system clock, check data latched by the strobe latch section. Based on a comparison by an expected value comparison section and a determination by a delay determination section, the optimal strobe signal with the optimal delay is selected from among the delayed strobe signals produced in the strobe delay selection section. Then, data from the memory is delayed through delay circuits in a data delay selection section, thus obtaining a plurality of delayed data, and the optimal data with the optimal delay is selected from among the plurality of delayed data based on the comparison by the expected value comparison section and the determination by the delay determination section.

Abstract translation: 来自存储器的选通信号通过选通延迟选择部分的延迟电路被延迟，从而获得多个延迟的选通信号。 选通锁存部分与延迟的选通信号中的每一个同步地产生检查数据，并且系统锁存部分用系统时钟锁存由选通锁存部分锁存的数据。 基于期望值比较部分的比较和延迟确定部分的确定，从选通延迟选择部分中产生的延迟选通信号中选择具有最佳延迟的最佳选通信号。 然后，通过数据延迟选择部分中的延迟电路来延迟来自存储器的数据，从而获得多个延迟数据，并且基于预期的比较，从多个延迟数据中选择具有最佳延迟的最佳数据 值比较部分和延迟确定部分的确定。

公开(公告)号：US09559094B2

公开(公告)日：2017-01-31

申请号：US14724485

申请日：2015-05-28

Applicant: SOCIONEXT INC.

Inventor： Teruo Suzuki

IPC: H01L23/62 ,  H01L27/02

CPC classification number: H01L27/027 ,  H01L27/0255

Abstract: A semiconductor device includes a first semiconductor region that has an external profile including at least one corner, and that includes a semiconductor of a first conductivity type, and a first insulation region that surrounds an outer periphery of the first semiconductor region, and that includes an insulator that, at a corner portion corresponding to the corner, has a depth deeper than a depth at a location other than the corner portion. The semiconductor device further includes a second semiconductor region that surrounds an outer periphery of the first insulation region, and that includes a semiconductor of a second conductivity type, and a second insulation region that surrounds an outer periphery of the second semiconductor region, and that includes an insulator that is deeper than the depth of the first insulation region at the location other than the corner portion.

Abstract translation: 半导体器件包括：第一半导体区域，其具有包括至少一个角部的外部轮廓，并且包括第一导电类型的半导体;以及包围第一半导体区域的外周的第一绝缘区域， 在角部对应的角部具有深度比在角部以外的位置的深度更深的绝缘体。 半导体器件还包括第二半导体区域，该第二半导体区域包围第一绝缘区域的外周，并且包括第二导电类型的半导体和围绕第二半导体区域的外周的第二绝缘区域，并且包括 绝缘体比在角部以外的位置处的第一绝缘区域的深度更深。

公开(公告)号：US09553598B2

公开(公告)日：2017-01-24

申请号：US14850472

申请日：2015-09-10

Applicant: Socionext Inc.

Inventor： Takeshi Nozaki

IPC: H03M1/06 ,  H03M1/08 ,  H03M1/12

CPC classification number: H03M1/0604 ,  H03M1/0836 ,  H03M1/1215

Abstract: A time-interleaved analog-to-digital converter that samples an analog input signal at a sampling frequency and converts the analog input signal into a digital output signal is enabled to perform correction processing on an error by: converting the analog input signal into the digital output signal by a plurality of analog-to-digital conversion circuits in a time-interleaved manner; and performing gain correction processing and skew correction processing with respect to the analog-to-digital conversion circuit, on the basis of a mixed signal, the mixed signal being obtained by mixing an output signal from the analog-to-digital conversion circuit with a signal made by shifting a phase of the output signal by π/2.

Abstract translation: 以采样频率对模拟输入信号进行采样并将模拟输入信号转换成数字输出信号的时间交替模数转换器能够通过以下方式对模拟输入信号进行转换：将模拟输入信号转换为数字 以时间交织方式由多个模数转换电路输出信号; 基于混合信号对模数转换电路进行增益校正处理和偏斜校正处理，混合信号是通过将来自模数转换电路的输出信号与 通过将输出信号的相位移位π/ 2而产生的信号。

公开(公告)号：US09547330B2

公开(公告)日：2017-01-17

申请号：US14049039

申请日：2013-10-08

Applicant: SOCIONEXT INC.

Inventor： Masaki Okada

IPC: G06F13/36 ,  G06F1/08 ,  G06F13/364 ,  G06F1/32

CPC classification number: G06F1/08 ,  G06F1/3237 ,  G06F1/324 ,  G06F13/364 ,  Y02D10/128

Abstract: A processor includes a plurality of processing units. A plurality of first arbitration units each arbitrate request signals output from at least two of the processing units to generate a first arbitration signal. A second arbitration unit arbitrates first arbitration signals output from the first arbitration units to generate a second arbitration signal. A plurality of clock controllers, arranged in correspondence with the first arbitration units, each generate a clock signal supplied to a corresponding first arbitration unit and the processing units coupled to the corresponding first arbitration unit. A control unit determines whether or not to operate each processing unit in accordance with an operation state of the processor and generates control information according to the determination result. Each of the clock controllers supplies or stops the clock signal or changes a frequency of the clock signal in accordance with the control information.

Abstract translation: 处理器包括多个处理单元。 多个第一仲裁单元各自仲裁从至少两个处理单元输出的请求信号以产生第一仲裁信号。 第二仲裁单元仲裁从第一仲裁单元输出的第一仲裁信号以产生第二仲裁信号。 与第一仲裁单元相对应地布置的多个时钟控制器各自产生提供给相应的第一仲裁单元的时钟信号，以及耦合到对应的第一仲裁单元的处理单元。 控制单元根据处理器的操作状态确定是否操作每个处理单元，并根据确定结果产生控制信息。 每个时钟控制器根据控制信息提供或停止时钟信号或改变时钟信号的频率。

公开(公告)号：US20170012006A1

公开(公告)日：2017-01-12

申请号：US15276390

申请日：2016-09-26

Applicant: SOCIONEXT INC.

Inventor： Yoshihiro OKUMURA ,  Yukio HIRAOKA ,  Shinichirou YONEYAMA ,  Miki YAMANAKA

IPC: H01L23/58 ,  H01L29/06

CPC classification number: H01L23/585 ,  H01L21/76224 ,  H01L23/5225 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A high-resistance region is formed right under a seal ring by irradiating a semiconductor substrate with hydrogen ions or helium ions. The high-resistance region has a greater thickness than an isolation insulating layer formed as a shallow trench isolation (STI) region on the surface of the semiconductor substrate. As a result, a semiconductor integrated circuit including a seal ring achieving excellent high-frequency isolation is provided.

Abstract translation: 通过用氢离子或氦离子照射半导体衬底，在密封环正下方形成高电阻区域。 高电阻区域的厚度大于在半导体衬底的表面上形成为浅沟槽隔离（STI）区域的隔离绝缘层。 结果，提供了包括实现优异的高频隔离的密封环的半导体集成电路。

公开(公告)号：US20160380638A1

公开(公告)日：2016-12-29

申请号：US15143080

申请日：2016-04-29

Applicant: SOCIONEXT INC.

Inventor： Makoto KUMAZAWA

IPC: H03L7/08 ,  H03L7/081 ,  H03M9/00 ,  H03L7/091

CPC classification number: H03L7/0807 ,  H03K5/135 ,  H03K5/26 ,  H03L7/0814 ,  H03L7/091 ,  H03L7/093 ,  H03M9/00 ,  H04L7/0025 ,  H04L7/0083 ,  H04L7/033 ,  H04L7/0337

Abstract: A CDR control circuit detects a phase shift of input data that is taken in with a phase-adjusted clock, and generates phase control data that controls the phase of the clock based on the detected phase shift, the CDR control circuit includes a change detection circuit that detects an over-change in the phase shift; and a selection circuit that outputs the phase shift before the change, which is the phase shift before the time of detection of the over-change, as the phase shift for a predetermined period of time at the time of detection of the over-change, wherein during the predetermined period of time, the phase control data is generated based on the phase shift before change.

Abstract translation: CDR控制电路检测相位调整时钟输入的输入数据的相移，根据检测出的相移产生控制时钟的相位的相位控制数据，CDR控制电路包括变化检测电路 其检测相移中的过度变化; 以及选择电路，其在检测到所述过度变化之前将预变化之前的相移作为所述相移输出预定时间段，所述相移是所述过度变化检测之前的相移， 其特征在于，在所述规定时间期间，根据变更前的相移来生成所述相位控制数据。