公开(公告)号：US07535723B2

公开(公告)日：2009-05-19

申请号：US10729710

申请日：2003-12-05

Applicant: Yakov Belopolsky

Inventor： Yakov Belopolsky

IPC: H05K7/00

CPC classification number: H05K3/3415 ,  H01L2224/16225 ,  H01L2924/00014 ,  H05K3/244 ,  H05K3/303 ,  H05K3/3436 ,  H05K3/3447 ,  H05K3/3463 ,  H05K2201/09781 ,  H05K2201/10659 ,  H05K2201/10734 ,  H05K2203/047 ,  H05K2203/167 ,  Y02P70/613 ,  Y10T29/49004 ,  Y10T29/49121 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49165 ,  Y10T29/49222 ,  H01L2224/0401

Abstract: Methods for mounting electrical components on a substrate and securely retaining the components are described. The methods include altering solder paste compositions, interposed between component retentive pins and retentive through holes, during a reflow process. Electronic assemblies including circuit boards and electrical components mounted thereto are also described. In one of the electronic assembly embodiments, materials originally associated with a mounted electrical component migrate into solder paste coupling the electrical component to the circuit board.

Abstract translation: 描述了将电气部件安装在基板上并可靠地保持部件的方法。 所述方法包括在回流过程期间改变介于组分保持性针和保持性通孔之间的焊膏组合物。 还描述了包括电路板和安装在其上的电气部件的电子组件。 在电子组装实施例之一中，最初与安装的电气部件相关联的材料迁移到将电气部件连接到电路板的焊膏中。

公开(公告)号：US20080291602A1

公开(公告)日：2008-11-27

申请号：US11753090

申请日：2007-05-24

Applicant: Daniel Devoe

Inventor： Daniel Devoe

IPC: H01G4/232 ,  B23P19/00

CPC classification number: H01G4/232 ,  H01G4/38 ,  H01G13/006 ,  H05K1/0203 ,  H05K3/3426 ,  H05K3/3447 ,  H05K2201/10469 ,  H05K2201/10537 ,  H05K2201/10636 ,  H05K2201/10659 ,  H05K2201/10946 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/53174

Abstract: A capacitor device, which is mountable on a substrate, has an electrically conductive bottom lead frame with a bottom plate mountable substantially parallel to, and in contact with, the substrate and an electrically conductive top lead frame having a top plate spaced apart from the bottom plate and a first transition portion having a first end connected to the top plate and a second end, opposite the first end, electrically connectable to the substrate. Multilayer capacitors are mounted between the top plate and the bottom plate. The capacitors have opposed end terminations electrically connected to the top and bottom plates, such that internal electrode plates are substantially nonparallel to the substrate.

Abstract translation: 可安装在基板上的电容器装置具有导电底部引线框架，其具有可安装为基本上平行于基板并与其接触的底板，以及导电顶部引线框架，其具有与底部间隔开的顶板 板和第一过渡部分，其具有连接到顶板的第一端和与第一端相对的第二端，其可电连接到基板。 多层电容器安装在顶板和底板之间。 电容器具有电连接到顶板和底板的相对端端，使得内部电极板基本上不平行于衬底。

公开(公告)号：US07387516B2

公开(公告)日：2008-06-17

申请号：US11629852

申请日：2005-05-24

Applicant: Tatsuya Hayakawa ,  Tatsuya Oka

Inventor： Tatsuya Hayakawa ,  Tatsuya Oka

IPC: H01R12/00

CPC classification number: H05K7/026 ,  H01R9/2425 ,  H01R9/2466 ,  H05K1/144 ,  H05K3/3447 ,  H05K2201/10189 ,  H05K2201/10303 ,  H05K2201/10659

Abstract: Three printed boards are stored in a case, and a relay connector for connecting the three printed boards is mounted on the second printed board at the middle position. The relay connector is provided with a first terminal storing part, which is long in a vertical direction, and a short second terminal storing part. The relay connector connects a terminal pin of the first printed board at an upper position with a terminal pin of the third printed board at a lower position, via a long first relay terminal stored in the first terminal storing part, while connecting a terminal pin of the first printed board and/or the terminal pin of the third printed board with a conductor of the second printed board, via a short second relay terminal stored in the second terminal storing part.

Abstract translation: 三个印刷电路板被存放在壳体中，并且用于连接三个印刷电路板的中继连接器安装在中间位置的第二印刷电路板上。 中继连接器设置有在垂直方向上长的第一端子存储部和短的第二端子存储部。 继电器连接器通过存储在第一端子存储部分中的长的第一中继端子将位于第一印刷电路板的上部位置的端子销与第三印刷电路板的端子引脚连接在下部位置，同时连接 通过存储在第二终端存储部分中的短的第二中继终端，具有第二印刷电路板的导体的第三印刷电路板的第一印刷电路板和/或端子销。

公开(公告)号：US07242084B2

公开(公告)日：2007-07-10

申请号：US11139223

申请日：2005-05-27

Applicant: Chee Wai Wong ,  Cheng Siew Tay

Inventor： Chee Wai Wong ,  Cheng Siew Tay

IPC: H01L23/48

CPC classification number: H01L23/49811 ,  H01L23/49816 ,  H01L2224/16225 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K3/303 ,  H05K3/3421 ,  H05K3/3447 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/10303 ,  H05K2201/10318 ,  H05K2201/10598 ,  H05K2201/10659 ,  H05K2201/10734 ,  Y02P70/613

Abstract: Apparatuses and associated methods to improve integrated circuit packaging are generally described. More specifically, apparatuses and associated methods to improve solder joint reliability are described. In this regard, according to one example embodiment, one or more strengthening pin(s) are coupled to the periphery of a package substrate, the strengthening pin(s) capable of coupling to a circuit board.

Abstract translation: 通常描述用于改进集成电路封装的装置和相关方法。 更具体地，描述了提高焊点可靠性的装置和相关方法。 在这方面，根据一个示例实施例，一个或多个加强销耦合到封装基板的周边，加强销能够耦合到电路板。

公开(公告)号：US07185821B1

公开(公告)日：2007-03-06

申请号：US10614905

申请日：2003-07-07

Applicant: Sergio Camerlo ,  Yida Zou ,  Luca Cafiero ,  Gary L. Myers ,  Bobby Parizi ,  Hsing-Sheng Liang

Inventor： Sergio Camerlo ,  Yida Zou ,  Luca Cafiero ,  Gary L. Myers ,  Bobby Parizi ,  Hsing-Sheng Liang

IPC: G06K19/02

CPC classification number: H01L23/49816 ,  H01L23/49805 ,  H01L23/49861 ,  H01L23/50 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/3025 ,  H05K1/0263 ,  H05K3/222 ,  H05K3/325 ,  H05K3/3415 ,  H05K3/3421 ,  H05K2201/10189 ,  H05K2201/1031 ,  H05K2201/1053 ,  H05K2201/10659 ,  H05K2201/10734 ,  H05K2201/10946 ,  Y02P70/611 ,  Y02P70/613

Abstract: An electronic interconnection system for delivering high-current power and ground voltages using a non-bottom side of a chip package substrate. The system includes a printed wiring board (PWB), a chip package, and a bridge lead. The PWB has at least a first and a second contact pad. The chip package includes a chip and a package substrate. The chip is mounted onto the package substrate and the package substrate has a bottom surface having at least a first contact pad and a second surface having at least a second contact pad. The first contact pad of the PWB and the first contact pad of the package substrate are coupled together. The bridge lead couples the second contact pad of the PWB with the second contact pad of the package substrate. The bridge lead may be selected from styles including flying lead, edge wiping, top wiping, and double wiping.

Abstract translation: 一种用于使用芯片封装衬底的非底侧提供大电流电源和接地电压的电子互连系统。 该系统包括印刷电路板（PWB），芯片封装和桥接引线。 PWB至少具有第一和第二接触垫。 芯片封装包括芯片和封装衬底。 芯片安装在封装衬底上，封装衬底具有至少第一接触焊盘和至少具有第二接触焊盘的第二表面的底表面。 PWB的第一接触焊盘和封装衬底的第一接触焊盘耦合在一起。 桥引线将PWB的第二接触焊盘与封装衬底的第二接触焊盘耦合。 桥引线可以从包括飞铅，边缘擦拭，顶部擦拭和双重擦拭的样式中选择。

公开(公告)号：US20060267217A1

公开(公告)日：2006-11-30

申请号：US11139223

申请日：2005-05-27

Applicant: Chee Wong ,  Cheng Tay

Inventor： Chee Wong ,  Cheng Tay

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L23/49811 ,  H01L23/49816 ,  H01L2224/16225 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K3/303 ,  H05K3/3421 ,  H05K3/3447 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/10303 ,  H05K2201/10318 ,  H05K2201/10598 ,  H05K2201/10659 ,  H05K2201/10734 ,  Y02P70/613

Abstract: Apparatuses and associated methods to improve integrated circuit packaging are generally described. More specifically, apparatuses and associated methods to improve solder joint reliability are described. In this regard, according to one example embodiment, one or more strengthening pin(s) are coupled to the periphery of a package substrate, the strengthening pin(s) capable of coupling to a circuit board.

Abstract translation: 通常描述用于改进集成电路封装的装置和相关方法。 更具体地，描述了提高焊点可靠性的装置和相关方法。 在这方面，根据一个示例实施例，一个或多个加强销耦合到封装基板的周边，加强销能够耦合到电路板。

公开(公告)号：US20060231935A1

公开(公告)日：2006-10-19

申请号：US11402008

申请日：2006-04-12

Applicant: Koji Nishida

Inventor： Koji Nishida

IPC: H01L23/02

CPC classification number: H05K3/3442 ,  H01L23/49805 ,  H01L23/49816 ,  H01L24/81 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K3/0052 ,  H05K3/3436 ,  H05K3/403 ,  H05K3/42 ,  H05K2201/09181 ,  H05K2201/10659 ,  H05K2201/10734 ,  Y02P70/613

Abstract: In a semiconductor package including a wiring board having a top surface, a bottom surface and a side face. The bottom surface is divided into a central area, and a peripheral area surrounding the central area. A semiconductor chip is mounted on the top surface of the wiring board so as to be electrically connected to a wiring pattern layer of the wiring board. An array of metal balls is provided as electrode terminals in the central area on the bottom surface of the wiring board. A plurality of additional electrode terminals are provided in the peripheral area on the bottom surface and/or the side face of the wiring board.

Abstract translation: 在包括具有顶表面，底表面和侧面的布线板的半导体封装中。 底面分为中心区域和围绕中心区域的周边区域。 半导体芯片安装在布线板的顶表面上，以与布线板的布线图案层电连接。 金属球的阵列作为电极端子设置在布线基板的底面的中央区域。 多个附加电极端子设置在布线板的底面和/或侧面的周边区域中。

公开(公告)号：US20060228912A1

公开(公告)日：2006-10-12

申请号：US11388549

申请日：2006-03-24

Applicant: Danny Morlion ,  Steven Minich ,  Stephen Smith

Inventor： Danny Morlion ,  Steven Minich ,  Stephen Smith

IPC: H05K1/00

CPC classification number: H01R12/737 ,  H01R12/716 ,  H01R12/724 ,  H01R13/6585 ,  H05K1/0219 ,  H05K1/0237 ,  H05K1/114 ,  H05K1/115 ,  H05K1/14 ,  H05K3/308 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09627 ,  H05K2201/10189 ,  H05K2201/1059 ,  H05K2201/10659

Abstract: An orthogonal backplane connector systems having midplane footprints that provide for continuity of impedance and signal integrity through the midplane and allow for the same connector to be coupled to either side of the midplane. This design creates an orthogonal interconnect without taking up unnecessary PCB real estate. The midplane circuit board may include a first differential signal pair of electrically conductive vias disposed in a first direction, and a second differential signal pair of electrically conductive vias disposed in a second direction that is generally orthogonal to the first direction. The first and second differential signal pair of electrically conductive vias are electrically connected through the midplane circuit board. Each pair may be associated with and be located in between ground vias. A ground via that is large relative to the signal vias may be provided. The second signal vias may comprise a shared signal via, receiving a contact from respective connectors connected to each side of the midplane circuit board. The second signal vias may comprise partial signal vias, extending from one or more sides partially into the midplane circuit board. The signal pairs may be offset from a via array centerline formed by the ground vias to correspond with mating ends of signal contacts of an electrical connector that likewise jog away from a centerline of a respective contact column of the connector.

Abstract translation: 正交背板连接器系统具有中间面积，其通过中平面提供阻抗和信号完整性的连续性，并允许相同的连接器耦合到中平面的任一侧。 该设计创建了一个正交互连，而不占用不必要的PCB空间。 中间平面电路板可以包括沿第一方向设置的导电通孔的第一差分信号对和沿大致正交于第一方向的第二方向设置的第二导电通孔对。 导电通孔的第一和第二差分信号对通过中平面电路板电连接。 每对可以与地面通孔相关联并位于其间。 可以提供相对于信号通路较大的接地通孔。 第二信号通孔可以包括共享信号通孔，从连接到中平面电路板的每一侧的相应连接器接收触点。 第二信号通孔可以包括从一个或多个侧面部分地延伸到中平面电路板中的部分信号通路。 信号对可以从由接地通孔形成的通孔阵列中心线偏移，以对应于同样从连接器的相应接触柱的中心线移开的电连接器的信号触头的配合端。

公开(公告)号：US20060208357A1

公开(公告)日：2006-09-21

申请号：US11086922

申请日：2005-03-21

Applicant: Thorsten Meyer ,  Harry Hedler ,  Stephan Dobritz

Inventor： Thorsten Meyer ,  Harry Hedler ,  Stephan Dobritz

IPC: H01L23/48

CPC classification number: H01L24/13 ,  H01L23/3114 ,  H01L24/14 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13017 ,  H01L2224/131 ,  H01L2224/13191 ,  H01L2224/13541 ,  H01L2224/13551 ,  H01L2224/13566 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/14051 ,  H01L2224/14141 ,  H01L2224/14145 ,  H01L2224/14146 ,  H01L2224/14177 ,  H01L2224/14505 ,  H01L2224/17051 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H05K3/325 ,  H05K3/3436 ,  H05K2201/0314 ,  H05K2201/0367 ,  H05K2201/10659 ,  H05K2201/10734 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: The present invention relates to an integrated device comprising an electronic circuit chip, a solder contact structure to provide contact to the electronic circuit chip and an elastic contact structure to provide contact to the electronic circuit chip, wherein the solder contact structure and the elastic contact structure are arranged on a contacting surface of the integrated device.

Abstract translation: 本发明涉及一种集成装置，其包括电子电路芯片，提供与电子电路芯片的接触的焊接触点结构和用于提供与电子电路芯片的接触的弹性接触结构，其中焊料接触结构和弹性接触结构 布置在集成装置的接触表面上。

公开(公告)号：US20060139892A1

公开(公告)日：2006-06-29

申请号：US10543398

申请日：2003-12-18

Applicant: Cornelis Mies

Inventor： Cornelis Mies

IPC: H05K7/20

CPC classification number: H05K7/20518 ,  H05K1/0203 ,  H05K1/144 ,  H05K3/368 ,  H05K2201/10303 ,  H05K2201/10659

Abstract: An electronic appliance, such as a computer and the like, comprising a printed circuit board with printed circuits arranged thereon and electromagnetic components electrically connected thereto, as well as a heat dissipating arrangement for dissipating heat generated by the components to the surrounding atmosphere, a special feature being the fact that the heat dissipating arrangement comprises a heat sink with several separate thermal conductors which are thermically connected to the printed circuits, which thermal conductors can be arranged on the printed circuit board in various positions, each position corresponding to a predetermined heat dissipation direction.

Abstract translation: 诸如计算机等的电子设备包括布置有印刷电路的印刷电路板和与其电连接的电磁部件，以及用于将组件产生的热量散发到周围大气的散热装置，特别的 特征在于散热装置包括散热器，散热器具有几个独立的热导体，其热连接到印刷电路，这些热导体可以以各种位置布置在印刷电路板上，每个位置对应于预定的散热 方向。