公开(公告)号：US20230115986A1

公开(公告)日：2023-04-13

申请号：US18046134

申请日：2022-10-12

Applicant: Apple Inc.

Inventor： Jun Chung Hsu ,  Chih-Ming Chung ,  Jun Zhai ,  Yifan Kao ,  Young Doo Jeon ,  Taegui Kim

IPC: H01L23/00

Abstract: Semiconductor packaging substrates and processing sequences are described. In an embodiment, a packaging substrate includes a build-up structure, and a patterned metal contact layer partially embedded within the build-up structure and protruding from the build-up structure. The patterned metal contact layer may include an array of surface mount (SMT) metal bumps in a chip mount area, a metal dam structure or combination thereof.

公开(公告)号：US10522475B2

公开(公告)日：2019-12-31

申请号：US16142137

申请日：2018-09-26

Applicant: Apple Inc.

Inventor： Meng Chi Lee ,  Shakti S. Chauhan ,  Flynn P. Carson ,  Jun Chung Hsu ,  Tha-An Lin

IPC: H01L23/552 ,  H01L23/528 ,  H01L23/31 ,  H01L23/522 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00

Abstract: A system in package (SiP) is disclosed that uses an EMI shield to inhibit EMI or other electrical interference on the components within the SiP. A metal shield may be formed on an upper surface of an encapsulant encapsulating the SiP. The metal shield may be electrically coupled to a ground layer in a printed circuit board (PCB) to form the EMI shield around the SiP. The metal shield may be electrically coupled to the ground layer using one or more conductive structures located in the encapsulant. The conductive structures may be located on a perimeter of the components in the SiP. The conductive structures may provide a substantially vertical connection between the substrate and the shield on the upper surface of the encapsulant.

公开(公告)号：US20190027445A1

公开(公告)日：2019-01-24

申请号：US16142137

申请日：2018-09-26

Applicant: Apple Inc.

Inventor： Meng Chi Lee ,  Shakti S. Chauhan ,  Flynn P. Carson ,  Jun Chung Hsu ,  Tha-An Lin

IPC: H01L23/552 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/552 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81

Abstract: A system in package (SiP) is disclosed that uses an EMI shield to inhibit EMI or other electrical interference on the components within the SiP. A metal shield may be formed on an upper surface of an encapsulant encapsulating the SiP. The metal shield may be electrically coupled to a ground layer in a printed circuit board (PCB) to form the EMI shield around the SiP. The metal shield may be electrically coupled to the ground layer using one or more conductive structures located in the encapsulant. The conductive structures may be located on a perimeter of the components in the SiP. The conductive structures may provide a substantially vertical connection between the substrate and the shield on the upper surface of the encapsulant.

公开(公告)号：US20170135219A1

公开(公告)日：2017-05-11

申请号：US14935292

申请日：2015-11-06

Applicant: Apple Inc.

Inventor： Jun Chung Hsu ,  Flynn P. Carson ,  Kwan-Yu Lai

IPC: H05K3/00 ,  H05K1/11

CPC classification number: H01L21/568 ,  H01L21/4857 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16235 ,  H01L2224/16245 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K3/4682 ,  Y10T29/49156 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81

Abstract: Method of forming ultra thin coreless substrates are described. In an embodiment, the method utilizes a debond layer including high and low adhesion surface areas to the carrier substrate, and cutting through the low adhesion surface areas to remove a build-up structure from the carrier substrate. An electrical short layer may be formed as a part of or on the debond layer to facilitate electrical testing of the build-up structure prior to debonding, and aid in the formation a “known good” substrate on a support substrate.

公开(公告)号：US09570367B2

公开(公告)日：2017-02-14

申请号：US15050110

申请日：2016-02-22

Applicant: Apple Inc.

Inventor： Jun Chung Hsu ,  Jun Zhai

IPC: H01L23/52 ,  H01L29/40 ,  H01L23/13 ,  H01L21/768 ,  H01L23/12 ,  H01L23/48 ,  H01L25/065 ,  H01L25/00 ,  H01L23/498 ,  H01L21/48 ,  H01L25/10

CPC classification number: H01L23/13 ,  H01L21/4857 ,  H01L21/76802 ,  H01L23/12 ,  H01L23/481 ,  H01L23/49822 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/19106 ,  H01L2924/00

Abstract: A bottom package for a PoP (package-on-package) may be formed with a reinforcement layer supporting a thin or coreless substrate. The reinforcement layer may provide stiffness and rigidity to the substrate to increase the stiffness and rigidity of the bottom package and provide better handling of the substrate. The reinforcement layer may be formed using core material, a laminate layer, and a metal layer. The substrate may be formed on the reinforcement layer. The reinforcement layer may include an opening sized to accommodate a die. The die may be coupled to an exposed surface of the substrate in the opening. Metal filled vias through the reinforcement layer may be used to couple the substrate to a top package.

Abstract translation: 用于PoP（封装封装）的底部封装可以形成有支撑薄的或无芯的衬底的加强层。 加强层可以为基底提供刚度和刚度，以增加底部包装的刚度和刚性，并提供更好的基底处理。 加强层可以使用芯材，层压层和金属层形成。 衬底可以形成在加强层上。 加强层可以包括尺寸适于容纳模具的开口。 裸片可以在开口中耦合到衬底的暴露表面。 通过加强层的金属填充的通孔可以用于将衬底耦合到顶部封装。

公开(公告)号：US20150061142A1

公开(公告)日：2015-03-05

申请号：US14088736

申请日：2013-11-25

Applicant: Apple Inc.

Inventor： Jun Chung Hsu ,  Jun Zhai

IPC: H01L23/12 ,  H01L25/00 ,  H01L25/065 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L23/13 ,  H01L21/4857 ,  H01L21/76802 ,  H01L23/12 ,  H01L23/481 ,  H01L23/49822 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/19106 ,  H01L2924/00

Abstract: A bottom package for a PoP (package-on-package) may be formed with a reinforcement layer supporting a thin or coreless substrate. The reinforcement layer may provide stiffness and rigidity to the substrate to increase the stiffness and rigidity of the bottom package and provide better handling of the substrate. The reinforcement layer may be formed using core material, a laminate layer, and a metal layer. The substrate may be formed on the reinforcement layer. The reinforcement layer may include an opening sized to accommodate a die. The die may be coupled to an exposed surface of the substrate in the opening. Metal filled vias through the reinforcement layer may be used to couple the substrate to a top package.

Abstract translation: 用于PoP（封装封装）的底部封装可以形成有支撑薄的或无芯的衬底的加强层。 加强层可以为基底提供刚度和刚度，以增加底部包装的刚度和刚性，并提供更好的基底处理。 加强层可以使用芯材，层压层和金属层形成。 衬底可以形成在加强层上。 加强层可以包括尺寸适于容纳模具的开口。 裸片可以在开口中耦合到衬底的暴露表面。 通过加强层的金属填充的通孔可以用于将衬底耦合到顶部封装。

公开(公告)号：US11908819B2

公开(公告)日：2024-02-20

申请号：US18046134

申请日：2022-10-12

Applicant: Apple Inc.

Inventor： Jun Chung Hsu ,  Chih-Ming Chung ,  Jun Zhai ,  Yifan Kao ,  Young Doo Jeon ,  Taegui Kim

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L24/14 ,  H01L21/4846 ,  H01L21/563 ,  H01L23/498 ,  H01L24/11 ,  H01L24/13 ,  H01L24/25 ,  H01L24/26 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/11003 ,  H01L2224/11424 ,  H01L2224/11464 ,  H01L2224/11614 ,  H01L2224/13083 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/14517 ,  H01L2224/16112 ,  H01L2224/24996 ,  H01L2224/2501 ,  H01L2224/26155 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/73204 ,  H01L2224/83051

Abstract: Semiconductor packaging substrates and processing sequences are described. In an embodiment, a packaging substrate includes a build-up structure, and a patterned metal contact layer partially embedded within the build-up structure and protruding from the build-up structure. The patterned metal contact layer may include an array of surface mount (SMT) metal bumps in a chip mount area, a metal dam structure or combination thereof.

公开(公告)号：US20230402390A1

公开(公告)日：2023-12-14

申请号：US17806660

申请日：2022-06-13

Applicant: Apple Inc.

Inventor： Ryan Mesch ,  Jun Chung Hsu

IPC: H01L23/538 ,  H01L21/48

CPC classification number: H01L23/5383 ,  H01L23/5386 ,  H01L21/4857

Abstract: Improved redistribution layer structures for integrated circuit or system-on-chip (SoC) packages substrate are disclosed. Via landing pads and via interconnects in the redistribution layers are self-aligning with the centers of the vias aligning with the pads. This self-alignment may allow pads that terminate non-stacked vias to have decreased widths or diameters without extra capture space. The redistribution layers have vias with vertical or near vertical sidewalls. Vias may also have various shapes, widths, or lengths. Traces in the redistribution layers may have various lengths and shapes with lengths that may extend into layers routing the vias to provide increased metal density in the traces.

公开(公告)号：US20230092505A1

公开(公告)日：2023-03-23

申请号：US17482967

申请日：2021-09-23

Applicant: Apple Inc.

Inventor： Yikang Deng ,  Taegui Kim ,  Yifan Kao ,  Jun Chung Hsu

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L25/00

Abstract: An asymmetric stackup structure for an SoC package substrate is disclosed. The package substrate may include a substrate with one or more insulating material layers. A first recess may be formed in an upper surface of the substrate. The recess may be formed down to a conductive layer in the substrate. An integrated passive device may be positioned in the recess. A plurality of build-up layers may be formed on top of the substrate. At least one via path may be formed through the build-up layers and the substrate to connect contacts on the lower surface of the substrate to contacts on the upper surface of the build-up layers.

公开(公告)号：US20200381383A1

公开(公告)日：2020-12-03

申请号：US16423931

申请日：2019-05-28

Applicant: Apple Inc.

Inventor： Jun Chung Hsu ,  Chih-Ming Chung ,  Jun Zhai ,  Yifan Kao ,  Young Doo Jeon ,  Taegui Kim

IPC: H01L23/00

Abstract: Semiconductor packaging substrates and processing sequences are described. In an embodiment, a packaging substrate includes a build-up structure, and a patterned metal contact layer partially embedded within the build-up structure and protruding from the build-up structure. The patterned metal contact layer may include an array of surface mount (SMT) metal bumps in a chip mount area, a metal dam structure or combination thereof.