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    METHODS OF FORMING SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACT ELEMENTS AND THE RESULTING DEVICE
    11.
    发明申请
    METHODS OF FORMING SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACT ELEMENTS AND THE RESULTING DEVICE 有权
    形成具有自对准接触元件和结果器件的半导体器件的方法

    公开(公告)号：US20170077247A1

    公开(公告)日：2017-03-16

    申请号：US14526980

    申请日：2014-10-29

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Xiuyu Cai

    IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/41783 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/66515 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7851

    Abstract: One method disclosed includes forming a final gate structure in a gate cavity that is laterally defined by sidewall spacers, removing a portion of the sidewall spacers to define recessed sidewall spacers, removing a portion of the final gate structure to define a recessed final gate structure and forming an etch stop on the recessed sidewall spacers and the recessed final gate structure. A transistor device disclosed herein includes a final gate structure that has an upper surface positioned at a first height level above a surface of a substrate, sidewall spacers positioned adjacent the final gate structure, the sidewall spacers having an upper surface that is positioned at a second, greater height level above the substrate, an etch stop layer formed on the upper surfaces of the sidewall spacers and the final gate structure, and a conductive contact that is conductively coupled to a contact region of the transistor.

    Abstract translation: 所公开的一种方法包括在门腔中形成最终栅极结构，其由侧壁间隔件横向限定，去除侧壁间隔物的一部分以限定凹陷的侧壁间隔物，去除最终栅极结构的一部分以限定凹陷的最终栅极结构， 在凹陷的侧壁间隔件和凹入的最终栅极结构上形成蚀刻停止。 本文公开的晶体管器件包括最终栅极结构，其具有位于衬底表面上方的第一高度水平处的上表面，邻近最终栅极结构定位的侧壁间隔物，侧壁间隔物具有位于第二位置的上表面 在衬底上方的更高的高度级，形成在侧壁间隔物和最终栅极结构的上表面上的蚀刻停止层，以及导电耦合到晶体管的接触区域的导电接触。

    Reduced trench profile for a gate
    13.
    发明授权
    Reduced trench profile for a gate 有权
    降低了门的沟槽轮廓

    公开(公告)号：US09564501B2

    公开(公告)日：2017-02-07

    申请号：US14581741

    申请日：2014-12-23

    Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie ,  Chun-chen Yeh

    IPC: H01L21/336 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40

    CPC classification number: H01L29/4236 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42384 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7825 ,  H01L29/78654

    Abstract: The present disclosure is directed to a gate structure for a transistor. The gate structure is formed on a substrate and includes a trench. There are sidewalls that line the trench. The sidewalls have a first dimension at a lower end of the trench and a second dimension at an upper end of the trench. The first dimension being larger than the second dimension, such that the sidewalls are tapered from a lower region to an upper region. A high k dielectric liner is formed on the sidewalls and a conductive liner is formed on the high k dielectric liner. A conductive material is in the trench and is adjacent to the conductive liner. The conductive material has a first dimension at the lower end of the trench that is smaller than a second dimension at the upper end of the trench.

    Abstract translation: 本公开涉及晶体管的栅极结构。 栅极结构形成在衬底上并且包括沟槽。 有沟槽划线的侧壁。 侧壁在沟槽的下端具有第一尺寸，在沟槽的上端具有第二尺寸。 第一尺寸大于第二尺寸，使得侧壁从下部区域向上部区域逐渐变细。 在侧壁上形成高k电介质衬垫，并且在高k电介质衬垫上形成导电衬垫。 导电材料在沟槽中并且与导电衬垫相邻。 导电材料在沟槽的下端具有小于沟槽上端的第二尺寸的第一尺寸。

    Gate structure cut after formation of epitaxial active regions
    14.
    发明授权
    Gate structure cut after formation of epitaxial active regions 有权
    形成外延活性区后的门结构切割

    公开(公告)号：US09559009B2

    公开(公告)日：2017-01-31

    申请号：US14876212

    申请日：2015-10-06

    Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

    Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Johnathan E. Faltermeier ,  Ali Khakifirooz ,  Theodorus E. Standaert ,  Ruilong Xie

    IPC: H01L21/311 ,  H01L21/8234 ,  H01L29/417 ,  H01L27/088 ,  H01L29/08 ,  H01L21/84 ,  H01L29/66

    CPC classification number: H01L21/823437 ,  H01L21/31111 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/845 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/785

    Abstract: A gate structure straddling a plurality of semiconductor material portions is formed. Source regions and drain regions are formed in the plurality of semiconductor material portions, and a gate spacer laterally surrounding the gate structure is formed. Epitaxial active regions are formed from the source and drain regions by a selective epitaxy process. The assembly of the gate structure and the gate spacer is cut into multiple portions employing a cut mask and an etch to form multiple gate assemblies. Each gate assembly includes a gate structure portion and two disjoined gate spacer portions laterally spaced by the gate structure portion. Portions of the epitaxial active regions can be removed from around sidewalls of the gate spacers to prevent electrical shorts among the epitaxial active regions. A dielectric spacer or a dielectric liner may be employed to limit areas in which metal semiconductor alloys are formed.

    Abstract translation: 形成跨越多个半导体材料部分的栅极结构。 源极区域和漏极区域形成在多个半导体材料部分中，并且形成横向围绕栅极结构的栅极间隔物。 通过选择性外延工艺从源极和漏极区域形成外延有源区。 通过切割掩模和蚀刻将栅极结构和栅极间隔物的组装切成多个部分以形成多个栅极组件。 每个门组件包括栅极结构部分和由栅极结构部分横向隔开的两个分离的栅极间隔部分。 可以从栅极间隔物的侧壁的周围去除外延有源区的一部分，以防止外延有源区中的电短路。 可以使用电介质间隔物或电介质衬垫来限制形成金属半导体合金的区域。

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