公开(公告)号：US20180358307A1

公开(公告)日：2018-12-13

申请号：US16108272

申请日：2018-08-22

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Jing-Yao Chang ,  Tao-Chih Chang ,  Fang-Jun Leu ,  Wei-Kuo Han ,  Kuo-Shu Kao

IPC: H01L23/00

CPC classification number: H01L23/562 ,  H01L24/33 ,  H01L24/83 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/32503 ,  H01L2224/33505 ,  H01L2924/014 ,  H01L2924/3512

Abstract: An electronic package structure is provided. The electronic packaging structure includes a substrate, a conductive layer disposed on the substrate, an intermetallic compound disposed on the conductive layer, a stress buffering material disposed on the substrate and adjacent to the conductive layer, and an electronic device disposed on the conductive layer and the stress buffering material. The intermetallic compound is disposed between the electronic device and the conductive layer, between the electronic device and the stress buffering material, between the substrate and the stress buffering material, and between the conductive layer and the stress buffering material. A maximum thickness of the intermetallic compound disposed between the electronic device and the stress buffering material, between the substrate and the stress buffering material, and between the conductive layer and the stress buffering material is greater than the thickness of the intermetallic compound disposed between the electronic device and the conductive layer.

公开(公告)号：US20180233477A1

公开(公告)日：2018-08-16

申请号：US15487754

申请日：2017-04-14

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Jing-Yao Chang ,  Tao-Chih Chang ,  Fang-Jun Leu ,  Wei-Kuo Han ,  Kuo-Shu Kao

IPC: H01L23/00

CPC classification number: H01L24/29 ,  H01L24/05 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/29012 ,  H01L2224/29013 ,  H01L2224/29076 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/32245 ,  H01L2224/32503 ,  H01L2224/83192 ,  H01L2224/83204 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/8381 ,  H01L2924/3512 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: An electronic package structure is provided. The electronic packaging structure includes a substrate, a conductive layer disposed on the substrate, an intermetallic compound disposed on the conductive layer, a stress buffering material and an electronic device. The stress buffering material is disposed on the substrate and adjacent to the conductive layer. The electronic device is disposed on the intermetallic compound and the stress buffering material, and the electronic device is in contact with the intermetallic compound. The stress buffering material is adjacent to the conductive layer to have the conductive layer and the stress buffering material together serving as a stress buffer, so as to enhance the effect of stress buffering, thereby preventing a wafer from cracking due to stress.

公开(公告)号：US20180019178A1

公开(公告)日：2018-01-18

申请号：US15647264

申请日：2017-07-12

Applicant: Industrial Technology Research Institute

Inventor： Yu-Min Lin ,  Kuo-Shu Kao ,  Jing-Yao Chang ,  Tao-Chih Chang

IPC: H01L23/367 ,  H01L23/13 ,  H01L23/31 ,  H01L23/373 ,  H05K3/00 ,  H05K3/32 ,  H05K1/18 ,  H01L23/00 ,  H05K1/02 ,  H01L25/065 ,  H05K1/11 ,  H01L21/56 ,  H01L25/10 ,  H01L23/538 ,  H01L23/492 ,  H01L21/48

CPC classification number: H01L23/367 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/3735 ,  H01L23/492 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/24137 ,  H01L2224/24247 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2225/1023 ,  H01L2225/1094 ,  H01L2924/01029 ,  H01L2924/15153 ,  H01L2924/35 ,  H01L2924/37001 ,  H05K1/0203 ,  H05K1/0204 ,  H05K1/115 ,  H05K1/185 ,  H05K3/0047 ,  H05K3/108 ,  H05K3/32 ,  H05K3/4688 ,  H05K2201/066 ,  H05K2201/09827 ,  H05K2201/10416

Abstract: A chip packaging includes a substrate, a first chip, a molding material, a first circuit, and a second circuit. The substrate includes a bottom surface, a first top surface disposed above the bottom surface with a first height, and a second top surface disposed above the bottom surface with a second height. The first height is smaller than the second height. The first chip is disposed on the first top surface. The molding material is disposed on the substrate and covers the first chip. The first and second circuits are disposed on the molding material, and are respectively and electrically connected to the first chip and the second top surface of the substrate. The substrate is made of copper material with huge area and has the properties of high current withstand capacity and high thermal efficiency. The second top surface protects the first chip from damage.

公开(公告)号：US09308603B2

公开(公告)日：2016-04-12

申请号：US13855719

申请日：2013-04-03

Applicant: Industrial Technology Research Institute

Inventor： Kuo-Shu Kao ,  Tao-Chih Chang ,  Wen-Chih Chen

IPC: B32B15/20 ,  B23K35/24 ,  B32B15/01 ,  B23K35/28 ,  B23K35/30 ,  H01L23/495 ,  H01L23/00 ,  H01L23/373 ,  H01L25/065

CPC classification number: B23K35/24 ,  B23K35/282 ,  B23K35/3013 ,  B23K35/302 ,  B32B15/01 ,  B32B15/018 ,  H01L23/3735 ,  H01L23/49513 ,  H01L23/49582 ,  H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/0345 ,  H01L2224/04026 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/2612 ,  H01L2224/27826 ,  H01L2224/291 ,  H01L2224/29118 ,  H01L2224/29561 ,  H01L2224/29565 ,  H01L2224/29582 ,  H01L2224/29583 ,  H01L2224/29639 ,  H01L2224/29644 ,  H01L2224/29647 ,  H01L2224/29663 ,  H01L2224/29664 ,  H01L2224/29669 ,  H01L2224/29673 ,  H01L2224/29676 ,  H01L2224/29678 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32503 ,  H01L2224/32507 ,  H01L2224/83007 ,  H01L2224/8309 ,  H01L2224/83101 ,  H01L2224/83203 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/83815 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/15787 ,  Y10T428/12792 ,  H01L2924/00015 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/0105 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01076 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A solder and a solder joint structure formed by the solder are provided. The solder includes a zinc-based material, a copper film, and a noble metal film. The copper film completely covers the surface of the zinc-based material. The noble metal film completely covers the copper film. The solder joint structure includes a zinc-based material and an intermetallic layer. The intermetallic layer consists of zinc and noble metal and completely covers the surface of the zinc-based material.

Abstract translation: 提供由焊料形成的焊料和焊点结构。 焊料包括锌基材料，铜膜和贵金属膜。 铜膜完全覆盖锌基材料的表面。 贵金属膜完全覆盖铜膜。 焊接结构包括锌基材料和金属间化合物层。 金属间层由锌和贵金属组成，并完全覆盖锌基材料的表面。