公开(公告)号：US20150061144A1

公开(公告)日：2015-03-05

申请号：US14476241

申请日：2014-09-03

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Irmgard Escher-Poeppel ,  Juergen Hoegerl ,  Olaf Hohlfeld ,  Peter Kanschat

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L25/07 ,  H01L25/00

CPC classification number: H01L23/562 ,  H01L21/56 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L23/051 ,  H01L23/3107 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/24 ,  H01L24/33 ,  H01L24/72 ,  H01L24/82 ,  H01L24/90 ,  H01L24/96 ,  H01L24/97 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/03002 ,  H01L2224/06181 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/29011 ,  H01L2224/33181 ,  H01L2224/82039 ,  H01L2224/96 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/35 ,  H01L2924/00

Abstract: A semiconductor arrangement includes upper and lower contact plates and basic chip assemblies. Each chip assembly has a semiconductor chip having a semiconductor body with upper and lower spaced apart sides. An individual upper main electrode and an individual control electrode are arranged on the upper side. The chip assemblies have either respectively a separate lower main electrode arranged on the lower side of the semiconductor chip of the corresponding basic chip assembly, or a common lower main electrode, which for each of the chip assemblies is arranged on the lower side of the semiconductor body of that chip assembly. An electrical current between the individual upper main electrode and the individual or common lower main electrode is controllable by its control electrode. The chip assemblies are connected to one another with a material bonded connection by a dielectric embedding compound, forming a solid assembly.

Abstract translation: 半导体装置包括上和下接触板和基本芯片组件。 每个芯片组件具有半导体芯片，半导体芯片具有上部和下部间隔开的侧面的半导体本体。 单独的上主电极和单独的控制电极设置在上侧。 芯片组件分别具有布置在相应的基本芯片组件的半导体芯片的下侧上的单独的下部主电极或共同的下部主电极，其中每个芯片组件布置在半导体的下侧 该芯片组件的主体。 各个上主电极和单个或公共下主电极之间的电流可由其控制电极控制。 芯片组件通过电介质嵌入化合物的材料结合连接彼此连接，形成固体组件。

公开(公告)号：US20130134572A1

公开(公告)日：2013-05-30

申请号：US13749006

申请日：2013-01-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Andreas Lenniger ,  Andre Uhlemann ,  Olaf Hohlfeld

IPC: H01L23/367 ,  H01L21/50

CPC classification number: H01L23/367 ,  H01L21/50 ,  H01L23/24 ,  H01L23/3135 ,  H01L23/3677 ,  H01L23/3735 ,  H01L23/3736 ,  H01L23/4006 ,  H01L23/473 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L25/072 ,  H01L2224/291 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40227 ,  H01L2224/40247 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48132 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83455 ,  H01L2224/83464 ,  H01L2224/83801 ,  H01L2224/8382 ,  H01L2224/8384 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/85205 ,  H01L2224/8584 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/013 ,  H01L2924/00013 ,  H01L2224/83205 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A semiconductor device includes a semiconductor chip joined with a substrate and a base plate joined with the substrate. The base plate includes a first metal layer clad to a second metal layer. The second metal layer is deformed to provide a pin-fin or fin cooling structure. The second metal layer has a sub-layer that has no pins and no pin-fins. The first metal layer has a first thickness and the sub-layer has a second thickness. The ratio between the first thickness and the second thickness is at least 4:1.

Abstract translation: 半导体器件包括与衬底连接的半导体芯片和与衬底接合的基板。 基板包括包覆到第二金属层的第一金属层。 第二金属层变形以提供销鳍或翅片冷却结构。 第二金属层具有没有引脚而没有引脚鳍的子层。 第一金属层具有第一厚度，并且子层具有第二厚度。 第一厚度与第二厚度之比至少为4:1。

公开(公告)号：US11557522B2

公开(公告)日：2023-01-17

申请号：US17366870

申请日：2021-07-02

Applicant: Infineon Technologies AG

Inventor： Alexander Roth ,  Olaf Hohlfeld

IPC: H01L23/24 ,  H01L23/053 ,  H01L21/56 ,  H01L23/29 ,  H01L21/54 ,  H01L23/00

Abstract: A method is disclosed for producing a power semiconductor module that includes a substrate, at least one semiconductor body, a connecting element and a contact element. The method includes: arranging the substrate in a housing having walls; at least partly filling a capacity formed by the walls of the housing and the substrate with an encapsulation material; hardening the encapsulation material to form a hard encapsulation; and closing the housing, wherein the contact element extends from the connecting element through an interior of the housing and through an opening in a cover of the housing to an outside of the housing in a direction perpendicular to a first surface of a first metallization layer of the substrate.

公开(公告)号：US11322451B2

公开(公告)日：2022-05-03

申请号：US16249172

申请日：2019-01-16

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Juergen Hoegerl ,  Gottfried Beer ,  Magdalena Hoier ,  Georg Meyer-Berg

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/373 ,  H01L23/498

Abstract: A power semiconductor module includes a power semiconductor die attached to the first metallized side, a passive component attached to the first metallized side, a first isolation layer encapsulating the power semiconductor die and the passive component, a first structured metallization layer on the first isolation layer, and a first plurality of electrically conductive vias extending through the first isolation layer from the first structured metallization layer to the power semiconductor die and the passive component.

公开(公告)号：US20200083138A1

公开(公告)日：2020-03-12

申请号：US16567383

申请日：2019-09-11

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld

IPC: H01L23/373 ,  H05K7/20 ,  H01L23/367 ,  H01L21/48

Abstract: A power semiconductor module arrangement includes a heat sink, a substrate arrangement arranged on the heat sink in a vertical direction, a heat-conducting paste arranged between a surface of the substrate arrangement and a surface of the heat sink in the vertical direction, wherein a plurality of thermally conducting particles is evenly distributed within the heat-conducting paste, and a plurality of whiskers or fibers. Each of the plurality of whiskers or fibers has a first end and a second end. The first end of each of the plurality of whiskers or fibers is inseparably connected to either the surface of the substrate arrangement or to the surface of the heat sink.

公开(公告)号：US10211158B2

公开(公告)日：2019-02-19

申请号：US14529371

申请日：2014-10-31

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Juergen Hoegerl ,  Gottfried Beer ,  Magdalena Hoier ,  Georg Meyer-Berg

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31 ,  H01L23/373 ,  H01L23/498

Abstract: A power semiconductor module includes a direct copper bonded (DCB) substrate having a ceramic substrate, a first copper metallization bonded to a first main surface of the ceramic substrate and a second copper metallization bonded to a second main surface of the ceramic substrate opposite the first main surface. The power semiconductor module further includes a power semiconductor die attached the first copper metallization, a passive component attached the first copper metallization, a first isolation layer encapsulating the power semiconductor die and the passive component, a first structured metallization layer on the first isolation layer, and a first plurality of electrically conductive vias extending through the first isolation layer from the first structured metallization layer to the power semiconductor die and the passive component. An integrated power module and a method of manufacturing the integrated power module are also provided.

公开(公告)号：US10096584B2

公开(公告)日：2018-10-09

申请号：US15337733

申请日：2016-10-28

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Guido Boenig ,  Irmgard Escher-Poeppel ,  Edward Fuergut ,  Martin Gruber ,  Thorsten Meyer

IPC: H01L21/00 ,  H01L25/00 ,  H01L21/50 ,  H01L21/56 ,  H01L23/14 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/07 ,  H01L21/60

Abstract: In order to produce a power semiconductor module, a circuit carrier is populated with a semiconductor chip and with an electrically conductive contact element. After populating, the semiconductor chip and the contact element are embedded into a dielectric embedding compound, and the contact element is exposed. In addition, an electrically conductive base layer is produced which electrically contacts the exposed contact element and which bears on the embedding compound and the exposed contact element. A prefabricated metal film is applied to the base layer by means of an electrically conductive connection layer.

公开(公告)号：US20170287880A1

公开(公告)日：2017-10-05

申请号：US15470960

申请日：2017-03-28

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Holger Doepke ,  Olaf Hohlfeld ,  Michael Juerss

IPC: H01L25/07 ,  H01L23/00 ,  H01L23/29 ,  H01L21/52 ,  H01L21/56

CPC classification number: H01L25/072 ,  H01L21/52 ,  H01L21/563 ,  H01L21/565 ,  H01L23/295 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/552 ,  H01L23/562 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/181 ,  H05K3/282 ,  H05K2201/09872 ,  H05K2203/1377 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A method for fabricating an electronic device package includes providing a carrier, disposing a semiconductor chip onto the carrier, the semiconductor chip having a contact pad on a main face thereof remote from the carrier, applying a contact element onto the contact pad, applying a dielectric layer on the carrier, the semiconductor chip, and the contact element, and applying an encapsulant onto the dielectric layer.

公开(公告)号：US20170125395A1

公开(公告)日：2017-05-04

申请号：US15337733

申请日：2016-10-28

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Guido Boenig ,  Irmgard Escher-Poeppel ,  Edward Fuergut ,  Martin Gruber ,  Thorsten Meyer

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/14 ,  H01L21/50 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L23/538

CPC classification number: H01L25/50 ,  H01L21/50 ,  H01L21/56 ,  H01L21/561 ,  H01L23/142 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/072 ,  H01L2021/60015 ,  H01L2021/60022 ,  H01L2021/60277 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/214 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/4813 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48245 ,  H01L2224/73267 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/92244 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/10344 ,  H01L2924/1301 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/19107 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2224/85399

Abstract: In order to produce a power semiconductor module, a circuit carrier is populated with a semiconductor chip and with an electrically conductive contact element. After populating, the semiconductor chip and the contact element are embedded into a dielectric embedding compound, and the contact element is exposed. In addition, an electrically conductive base layer is produced which electrically contacts the exposed contact element and which bears on the embedding compound and the exposed contact element. A prefabricated metal film is applied to the base layer by means of an electrically conductive connection layer.

公开(公告)号：US20160126212A1

公开(公告)日：2016-05-05

申请号：US14926615

申请日：2015-10-29

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Juergen Hoegerl

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/72 ,  H01L21/568 ,  H01L23/051 ,  H01L23/3107 ,  H01L23/3736 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0655 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/24137 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00012

Abstract: One aspect of the invention relates to a chip assemblage. The latter comprises a number of semiconductor chips, each of which has a semiconductor body having an underside, and also a top side, which is spaced apart from the underside in a vertical direction. A top main electrode is arranged on the top side and a bottom main electrode is arranged on the underside. Moreover, each of the semiconductor chips has a control electrode, by means of which an electric current between the top main electrode and the bottom main electrode can be controlled. The semiconductor chips are connected to one another by a dielectric embedding compound to form a solid assemblage. The chip assemblage additionally comprises a common control terminal, and a common reference potential terminal. The common control terminal is electrically conductively connected to each of the control electrodes via a control electrode interconnection structure, and the common reference potential terminal is electrically conductively connected to each of the first main electrodes via a main electrode interconnection structure. Moreover, a dedicated, electrically conductive top compensation lamina is present for each of the semiconductor chips, said top compensation lamina being arranged on that side of the top main electrode which faces away from the semiconductor body and being cohesively and electrically conductively connected to the top main electrode.

Abstract translation: 本发明的一个方面涉及一种芯片组合。 后者包括多个半导体芯片，每个半导体芯片具有一个具有下侧的半导体主体，以及一个在垂直方向上与下侧隔开的顶侧。 顶部主电极设置在顶侧，底部主电极设置在下侧。 此外，每个半导体芯片具有控制电极，通过该控制电极可以控制顶部主电极和底部主电极之间的电流。 半导体芯片通过电介质嵌入化合物彼此连接以形成固体组合物。 芯片组合还包括公共控制端子和公共参考电位端子。 公共控制端子经由控制电极互连结构导电地连接到每个控制电极，并且公共参考电位端子经由主电极互连结构导电地连接到每个第一主电极。 此外，对于每个半导体芯片，存在专用的导电顶部补偿层，所述顶部补偿层布置在顶部主电极的背离半导体主体的一侧并且内部并且导电地连接到顶部 主电极