公开(公告)号：US20240087971A1

公开(公告)日：2024-03-14

申请号：US17943915

申请日：2022-09-13

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Gang DUAN ,  Srinivas V. PIETAMBARAM ,  Kristof DARMAWIKARTA ,  Jeremy D. ECTON ,  Suddhasattwa NAD ,  Hiroki TANAKA ,  Pooya TADAYON

IPC: H01L23/15 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/15 ,  H01L23/5381 ,  H01L23/5384 ,  H01L24/16 ,  H01L2224/16225

Abstract: Embodiments disclosed herein include interposers and methods of forming interposers. In an embodiment, an interposer comprises a substrate with a first surface and a second surface opposite from the first surface, where the substrate comprises glass. In an embodiment, the interposer further comprises a cavity into the first surface of the substrate, a via through the substrate below the cavity, a first pad in the cavity over the via, and a second pad on the second surface of the substrate under the via.

公开(公告)号：US20230197770A1

公开(公告)日：2023-06-22

申请号：US17559847

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Hiroki TANAKA ,  Kristof DARMAWIKARTA

IPC: H01L49/02 ,  H01L23/498 ,  H01G4/33 ,  H01G4/08 ,  H01G4/38

CPC classification number: H01L28/90 ,  H01L23/49822 ,  H01G4/33 ,  H01G4/08 ,  H01G4/38

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to electrically coupled trench capacitors within a substrate. The substrate may be part of an interposer, such as a glass interposer, where the trench capacitors deliver a high capacitance density close to one or more dies that are attached to a surface of the substrate. Portions of the trench capacitor may be a thin film capacitor at a surface of the substrate. The trenches extend from a first side of the substrate toward a second side of the substrate opposite the first side. Other embodiments may be described and/or claimed.

公开(公告)号：US20220406523A1

公开(公告)日：2022-12-22

申请号：US17350164

申请日：2021-06-17

Applicant: Intel Corporation

Inventor： Telesphor KAMGAING ,  Veronica STRONG ,  Neelam PRABHU GAUNKAR ,  Aleksandar ALEKSOV ,  Georgios C. DOGIAMIS ,  Hiroki TANAKA

IPC: H01G4/002

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to creating capacitors at the interface of a glass substrate. These capacitors may be three-dimensional (3-D) capacitors formed using trenches within the glass core of the substrate using laser-assisted etching techniques. A first electrode may be formed on the glass, including on the surface of trenches or other features etched in the glass, followed by a deposition of a dielectric material or a capacitive material. A second electrode may then be formed on top of the dielectric material. Other embodiments may be described and/or claimed.

公开(公告)号：US20210066447A1

公开(公告)日：2021-03-04

申请号：US16560647

申请日：2019-09-04

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Brandon C. MARIN ,  Jeremy ECTON ,  Hiroki TANAKA ,  Frank TRUONG

IPC: H01L49/02 ,  H01G4/008 ,  H01G4/12 ,  H01L21/48 ,  H01G4/28

Abstract: Embodiments herein relate to a capacitor device or a manufacturing process flow for creating a capacitor that includes nanoislands within a package. The capacitor a first conductive plate having a first side and a second side opposite the first side and a second conductive plate having a first side and a second side opposite the first side where the first side of the first conductive plate faces the first side of the second conductive plate. A first plurality of nanoislands is distributed on the first side of the first conductive plate and a second plurality of nanoislands is distributed on the first side of the second conductive plate, where the first conductive plate, the second conductive plate, and the first and second pluralities of nanoislands form a capacitor. The nanoislands may be applied to the conductive plates using a sputtering technique.

公开(公告)号：US20190355647A1

公开(公告)日：2019-11-21

申请号：US16527961

申请日：2019-07-31

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Hiroki TANAKA ,  Robert A. MAY ,  Kristof DARMAWIKARTA ,  Changhua LIU ,  Chung Kwang TAN ,  Srinivas PIETAMBARAM ,  Sri Ranga Sai BOYAPATI

IPC: H01L23/485 ,  H01L21/027 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/544

Abstract: Techniques that can assist with fabricating a package layer that includes a plurality of dual-damascene zero-misalignment-vias (dual-damascene ZMVs) and a trace between the dual-damascene ZMVs are described. The disclosed techniques allow for the dual-damascene ZMVs and their corresponding trace to be plated simultaneously in a single step or operation. As such, there is little or no misalignment between the dual-damascene ZMVs, the trace, and the metal pads connected to the ZMVs. In this way, one or more of the embodiments described herein can assist with reducing manufacturing costs, reducing development time of fabricating a package layer, and with increasing the I/O density in a semiconductor package.

公开(公告)号：US20240339381A1

公开(公告)日：2024-10-10

申请号：US18130582

申请日：2023-04-04

Applicant: Intel Corporation

Inventor： Hiroki TANAKA ,  Veronica STRONG ,  Henning BRAUNISCH ,  Haobo CHEN ,  Jeremy D. ECTON ,  Kristof DARMAWIKARTA ,  Brandon C. MARIN

IPC: H01L23/482 ,  H01L21/768 ,  H01L23/498

CPC classification number: H01L23/4821 ,  H01L21/76831 ,  H01L23/49827 ,  H01L23/49866 ,  H01L21/30604 ,  H05K2201/09218

Abstract: Embodiments disclosed herein include an interposer. In an embodiment, the interposer comprises a substrate, where the substrate comprises a glass layer. In an embodiment, a trace is on the substrate, where the trace has a bottom surface, sidewall surfaces, and a top surface. In an embodiment, the sidewall surfaces and the top surface are exposed to air. In an embodiment, a trench into the substrate is adjacent to at least one sidewall surface of the trace.

公开(公告)号：US20220190918A1

公开(公告)日：2022-06-16

申请号：US17119844

申请日：2020-12-11

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Kaveh HOSSEINI ,  Conor O'KEEFFE ,  Hiroki TANAKA

IPC: H04B10/2581 ,  H04B10/50 ,  H04B10/66 ,  G02F1/09 ,  G02F1/01 ,  G02B27/28

Abstract: Embodiments disclosed herein include photonics systems with a dual polarization module. In an embodiment, a photonics patch comprises a patch substrate, and a photonics die over a first surface of the patch substrate. In an embodiment, a multiplexer is over a second surface of the patch substrate. In an embodiment, a first optical path from the photonics die to the multiplexer is provided for propagating a first optical signal, and a second optical path from the photonics die to the multiplexer is provided for propagating a second optical signal. In an embodiment, a Faraday rotator is provided along the second optical path to convert the second optical signal from a first mode to a second mode before reaching the multiplexer.

公开(公告)号：US20190295951A1

公开(公告)日：2019-09-26

申请号：US15934343

申请日：2018-03-23

Applicant: Intel Corporation

Inventor： Kristof DARMAWIKARTA ,  Hiroki TANAKA ,  Robert MAY ,  Sameer PAITAL ,  Bai NIE ,  Jesse JONES ,  Chung Kwang Christopher TAN

IPC: H01L23/538 ,  H01L23/522 ,  H01L23/00

Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.

公开(公告)号：US20190169020A1

公开(公告)日：2019-06-06

申请号：US15832223

申请日：2017-12-05

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Kristof DARMAWIKARTA ,  Robert A. MAY ,  Changhua LIU ,  Hiroki TANAKA ,  Feras EID

IPC: B81B7/02 ,  B81C1/00 ,  H01L23/498

Abstract: A package substrate is provided which comprises: one or more first conductive contacts on a first surface; one or more second conductive contacts on a second surface opposite the first surface; a dielectric layer between the first and the second surfaces; and an embedded sensing or actuating element on the dielectric layer conductively coupled with one of the first conductive contacts, wherein the embedded sensing or actuating element comprises a fixed metal layer in the dielectric layer and a flexible metal layer suspended over the fixed metal layer by one or more metal supports on the dielectric layer. Other embodiments are also disclosed and claimed.

公开(公告)号：US20250112136A1

公开(公告)日：2025-04-03

申请号：US18374937

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Bohan SHAN ,  Jesse JONES ,  Zhixin XIE ,  Bai NIE ,  Shaojiang CHEN ,  Joshua STACEY ,  Mitchell PAGE ,  Brandon C. MARIN ,  Jeremy D. ECTON ,  Nicholas S. HAEHN ,  Astitva TRIPATHI ,  Yuqin LI ,  Edvin CETEGEN ,  Jason M. GAMBA ,  Jacob VEHONSKY ,  Jianyong MO ,  Makoyi WATSON ,  Shripad GOKHALE ,  Mine KAYA ,  Kartik SRINIVASAN ,  Haobo CHEN ,  Ziyin LIN ,  Kyle ARRINGTON ,  Jose WAIMIN ,  Ryan CARRAZZONE ,  Hongxia FENG ,  Srinivas Venkata Ramanuja PIETAMBARAM ,  Gang DUAN ,  Dingying David XU ,  Hiroki TANAKA ,  Ashay DANI ,  Praveen SREERAMAGIRI ,  Yi LI ,  Ibrahim EL KHATIB ,  Aaron GARELICK ,  Robin MCREE ,  Hassan AJAMI ,  Yekan WANG ,  Andrew JIMENEZ ,  Jung Kyu HAN ,  Hanyu SONG ,  Yonggang Yong LI ,  Mahdi MOHAMMADIGHALENI ,  Whitney BRYKS ,  Shuqi LAI ,  Jieying KONG ,  Thomas HEATON ,  Dilan SENEVIRATNE ,  Yiqun BAI ,  Bin MU ,  Mohit GUPTA ,  Xiaoying GUO

IPC: H01L23/498 ,  H01L23/15

Abstract: Embodiments disclosed herein include apparatuses with glass core package substrates. In an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface. A sidewall is between the first surface and the second surface, and the substrate comprises a glass layer. In an embodiment, a via is provided through the substrate between the first surface and the second surface, and the via is electrically conductive. In an embodiment, a layer in contact with the sidewall of the substrate surrounds a perimeter of the substrate.