公开(公告)号：US20210397084A1

公开(公告)日：2021-12-23

申请号：US17464393

申请日：2021-09-01

Applicant: Intel Corporation

Inventor： James M. BLACKWELL ,  Robert L. BRISTOL ,  Marie KRYSAK ,  Florian GSTREIN ,  Eungnak HAN ,  Kevin L. LIN ,  Rami HOURANI ,  Shane M. HARLSON

IPC: G03F7/00 ,  H01L21/027 ,  H01L21/768 ,  G03F7/40

Abstract: Lined photoresist structures to facilitate fabricating back end of line (BEOL) interconnects are described. In an embodiment, a hard mask has recesses formed therein, wherein liner structures are variously disposed each on a sidewall of a respective recess. Photobuckets comprising photoresist material are also variously disposed in the recesses. The liner structures variously serve as marginal buffers to mitigate possible effects of misalignment in the exposure of photoresist material to photons or an electron beam. In another embodiment, a recess has disposed therein a liner structure and a photobucket that are both formed by self-assembly of a photoresist-based block-copolymer.

公开(公告)号：US20210057337A1

公开(公告)日：2021-02-25

申请号：US16956251

申请日：2018-03-26

Applicant: Intel Corporation

Inventor： Eungnak HAN ,  Tayseer MAHDI ,  Rami HOURANI ,  Gurpreet SINGH ,  Florian GSTREIN

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  G03F7/20

Abstract: Multifunctional molecules for selective polymer formation on conductive surfaces, and the resulting structures, are described. In an example, an integrated circuit structure includes a lower metallization layer including alternating metal lines and dielectric lines above the substrate. A molecular brush layer is on the metal lines of the lower metallization layer, the molecular brush layer including multifunctional molecules. A triblock copolymer layer is above the lower metallization layer. The triblock copolymer layer includes a first segregated block component over the dielectric lines of the lower metallization layer, and alternating second and third segregated block components on the molecular brush layer on the metal lines of the lower metallization layer, where the third segregated block component is photosensitive.

公开(公告)号：US20200006427A1

公开(公告)日：2020-01-02

申请号：US16024684

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Noriyuki SATO ,  Kevin O'BRIEN ,  Eungnak HAN ,  Manish CHANDHOK ,  Gurpreet SINGH ,  Nafees KABIR ,  Kevin LIN ,  Rami HOURANI ,  Abhishek SHARMA ,  Hui Jae YOO

IPC: H01L27/24 ,  H01L45/00

Abstract: An integrated circuit structure includes a first material block comprising a first block insulator layer and a first multilayer stack on the first block insulator layer, the first multilayer stack comprising interleaved pillar electrodes and insulator layers. A second material block is stacked on the first material block and comprises a second block insulator layer, and a second multilayer stack on the second block insulator layer, the second multilayer stack comprising interleaved pillar electrodes and insulator layers. At least one pillar extends through the first material block and the second material block, wherein the at least one pillar has a top width at a top of the first and second material blocks that is greater than a bottom width at a bottom of the first and second material blocks.

公开(公告)号：US20180204797A1

公开(公告)日：2018-07-19

申请号：US15575808

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Kevin LIN ,  Robert Lindsey BRISTOL ,  James M. BLACKWELL ,  Rami HOURANI

IPC: H01L23/522 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/02282 ,  H01L21/31144 ,  H01L21/321 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/53209 ,  H01L23/53295

Abstract: Embodiments of the invention include an interconnect structure with a via and methods of forming such structures. In an embodiment, the interconnect structure comprises a first interlayer dielectric (ILD). A first interconnect line and a second interconnect line extend into the first ILD. According to an embodiment, a second ILD is positioned over the first interconnect line and the second interconnect line. A via may extend through the second ILD and electrically coupled to the first interconnect line. Additionally, embodiments of the invention include a portion of a bottom surface of the via being positioned over the second interconnect line. However, an isolation layer may be positioned between the bottom surface of the via and a top surface of the second interconnect line, according to an embodiment of the invention.

公开(公告)号：US20180130707A1

公开(公告)日：2018-05-10

申请号：US15573108

申请日：2015-06-18

Applicant: Intel Corporation

Inventor： Scott B. CLENDENNING ,  Martin M. MITAN ,  Timothy E. GLASSMAN ,  Flavio GRIGGIO ,  Grant M. KLOSTER ,  Kent N. FRASURE ,  Florian GSTREIN ,  Rami HOURANI

IPC: H01L21/768 ,  H01L21/285 ,  H01L21/311

CPC classification number: H01L21/76879 ,  C23C16/045 ,  H01L21/28 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/31144 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/76865 ,  H01L21/76876 ,  H01L29/66545 ,  H01L29/66795 ,  H01L2221/1063

Abstract: Bottom-up fill approaches for forming metal features of semiconductor structures, and the resulting structures, are described. In an example, a semiconductor structure includes a trench disposed in an inter-layer dielectric (ILD) layer. The trench has sidewalls, a bottom and a top. A U-shaped metal seed layer is disposed at the bottom of the trench and along the sidewalls of the trench but substantially below the top of the trench. A metal fill layer is disposed on the U-shaped metal seed layer and fills the trench to the top of the trench. The metal fill layer is in direct contact with dielectric material of the ILD layer along portions of the sidewalls of the trench above the U-shaped metal seed layer.

公开(公告)号：US20170330972A1

公开(公告)日：2017-11-16

申请号：US15527288

申请日：2014-12-19

Applicant: INTEL CORPORATION

Inventor： GRANT KLOSTER ,  SCOTT CLENDENNING ,  Rami HOURANI ,  SZUYA S. LIAO ,  PATRICIO E. ROMERO ,  FLORIAN GSTREIN

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/423 ,  H01L21/28 ,  H01L29/06 ,  H01L21/3105 ,  H01L21/311 ,  H01L29/786 ,  H01L23/498

CPC classification number: H01L29/7851 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/28194 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31133 ,  H01L21/32 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42368 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/786

Abstract: Methods of selectively depositing high-K gate dielectric on a semiconductor structure are disclosed. The method includes providing a semiconductor structure disposed above a semiconductor substrate. The semiconductor structure is disposed beside an isolation sidewall. A sacrificial blocking layer is then selectively deposited on the isolation sidewall and not on the semiconductor structure. Thereafter, a high-K gate dielectric is deposited on the semiconductor structure, but not on the sacrificial blocking layer. Properties of the sacrificial blocking layer prevent deposition of oxide material on its surface. A thermal treatment is then performed to remove the sacrificial blocking layer, thereby forming a high-K gate dielectric only on the semiconductor structure.

公开(公告)号：US20240047543A1

公开(公告)日：2024-02-08

申请号：US18382339

申请日：2023-10-20

Applicant: Intel Corporation

Inventor： Rami HOURANI ,  Richard VREELAND ,  Giselle ELBAZ ,  Manish CHANDHOK ,  Richard E. SCHENKER ,  Gurpreet SINGH ,  Florian GSTREIN ,  Nafees KABIR ,  Tristan A. TRONIC ,  Eungnak HAN

IPC: H01L29/423 ,  H01L29/78 ,  H01L23/522 ,  H01L29/417 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/4238 ,  H01L29/7851 ,  H01L23/5226 ,  H01L29/41775 ,  H01L27/0886 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823468 ,  H01L21/823431

Abstract: Contact over active gate structures with metal oxide cap structures are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a metal oxide cap structure thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on a portion of one or more of the metal oxide cap structures.

公开(公告)号：US20220102207A1

公开(公告)日：2022-03-31

申请号：US17549831

申请日：2021-12-13

Applicant: Intel Corporation

Inventor： Florian GSTREIN ,  Rami HOURANI ,  Gopinath BHIMARASETTI ,  James M. BLACKWELL

IPC: H01L21/768 ,  H01L21/308 ,  H01L23/528 ,  H01L21/033

Abstract: Bottom-up fill dielectric materials for semiconductor structure fabrication, and methods of fabricating bottom-up fill dielectric materials for semiconductor structure fabrication, are described. In an example, a method of fabricating a dielectric material for semiconductor structure fabrication includes forming a trench in a material layer above a substrate. A blocking layer is formed partially into the trench along upper portions of sidewalls of the trench. A dielectric layer is formed filling a bottom portion of the trench with a dielectric material up to the blocking layer. The blocking layer is removed. The forming the blocking layer, the forming the dielectric layer, and the removing the blocking layer are repeated until the trench is completely filled with the dielectric material.

公开(公告)号：US20200066521A1

公开(公告)日：2020-02-27

申请号：US16489331

申请日：2017-03-31

Applicant: INTEL CORPORATION

Inventor： Kevin LIN ,  Rami HOURANI ,  Elliot N. TAN ,  Manish CHANDHOK ,  Anant H. JAHAGIRDAR ,  Robert L. BRISTOL ,  Richard E. SCHENKER ,  Aaron Douglas LILAK

IPC: H01L21/033 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/32 ,  H01L21/3115

Abstract: A computing device including tight pitch features and a method of fabricating a computing device using colored spacer formation is disclosed. The computing device includes a memory and an integrated circuit coupled to the memory. The integrated circuit includes a first multitude of features above a substrate. The integrated circuit die includes a second multitude of features above the substrate. The first multitude of features and the second multitude of features are same features disposed in a first direction. The first multitude of features interleave with the second multitude of features. The first multitude of features has a first size and the second multitude of features has a second size.

公开(公告)号：US20200058548A1

公开(公告)日：2020-02-20

申请号：US16347507

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Eungnak HAN ,  Rami HOURANI ,  Florian GSTREIN ,  Gurpreet SINGH ,  Scott B. CLENDENNING ,  Kevin L. LIN ,  Manish CHANDHOK

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/033 ,  H01L23/522

Abstract: Selective hardmask-based approaches for conductive via fabrication are described. In an example, an integrated circuit structure includes a plurality of conductive lines in an inter-layer dielectric (ILD) layer above a substrate. The plurality of conductive lines includes alternating non-recessed conductive lines and recessed conductive lines. The non-recessed conductive lines are substantially co-planar with the ILD layer, and the recessed conductive lines are recessed relative to an uppermost surface of the ILD layer. A dielectric capping layer is in recess regions above the recessed conductive lines. A hardmask layer is over the non-recessed conductive lines but not over the dielectric capping layer of the recessed conductive lines. The hardmask layer differs in composition from the dielectric capping layer. A conductive via is in an opening in the dielectric capping layer and on one of the recessed conductive lines. A portion of the conductive via is on a portion of the hardmask layer.