公开(公告)号：US11056466B2

公开(公告)日：2021-07-06

申请号：US16552459

申请日：2019-08-27

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Christopher L. Rumer ,  Nitin Deshpande ,  Robert M. Nickerson

IPC: H01L23/48 ,  H01L23/52 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/54 ,  H01L23/04 ,  H01L25/10 ,  H01L23/498

Abstract: Systems and methods for improving heat distribution and heat removal efficiency in PoP semiconductor packages are provided. A PoP semiconductor package includes a first semiconductor package that is physically, communicably, and conductively coupled to a stacked second semiconductor package. A gap forms between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package. Additionally, interstitial gaps form between each of the PoP semiconductor packages disposed on an organic substrate. A curable fluid material, such as a molding compound, may be flowed both in the interstitial spaces between the PoP semiconductor packages and into the gap between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package.

公开(公告)号：US09691727B2

公开(公告)日：2017-06-27

申请号：US14686210

申请日：2015-04-14

Applicant: Intel Corporation

Inventor： Javier Soto Gonzalez ,  Charavana K. Gurumurthy ,  Robert M. Nickerson ,  Debendra Mallik

IPC: H05K3/46 ,  H05K3/40 ,  H05K3/34 ,  H05K3/28 ,  H05K3/24 ,  H05K3/20 ,  H05K3/00 ,  H05K1/11 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L24/17 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/2064 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/20644 ,  H05K1/113 ,  H05K3/0035 ,  H05K3/007 ,  H05K3/20 ,  H05K3/244 ,  H05K3/28 ,  H05K3/3457 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/096 ,  H05K2203/0152 ,  H05K2203/1536 ,  Y10T29/49147 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A microelectronic device includes a laminated mounting substrate including a die side and a land side with a surface finish layer disposed in a recess on the mounting substrate die side. An electrically conductive first plug is in contact with the surface finish layer and an electrically conductive subsequent plug is disposed on the mounting substrate land side and it is electrically coupled to the electrically conductive first plug and disposed directly below the electrically conductive first plug.

公开(公告)号：US12107082B2

公开(公告)日：2024-10-01

申请号：US18368424

申请日：2023-09-14

Applicant: Intel Corporation

Inventor： Russell K. Mortensen ,  Robert M. Nickerson ,  Nicholas R. Watts

IPC: H01L21/00 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/56 ,  H01L21/60 ,  H01L23/00 ,  H01L23/02 ,  H01L23/28 ,  H01L23/31 ,  H01L23/48 ,  H01L23/488 ,  H01L23/498 ,  H01L23/52 ,  H01L23/538 ,  H01L23/552 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/11 ,  H01L25/18 ,  H05K1/02 ,  H05K1/11 ,  H05K3/40

CPC classification number: H01L25/18 ,  H01L21/4846 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/17 ,  H01L24/43 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/89 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H05K1/113 ,  H05K3/4038 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/08238 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48472 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/143 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1511 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/381 ,  Y10T29/49124 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/48472 ,  H01L2224/48227 ,  H01L2924/00

Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

公开(公告)号：US11978730B2

公开(公告)日：2024-05-07

申请号：US17587664

申请日：2022-01-28

Applicant: Intel Corporation

Inventor： Russell K. Mortensen ,  Robert M. Nickerson ,  Nicholas R. Watts

IPC: H01L21/00 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/56 ,  H01L21/58 ,  H01L21/60 ,  H01L23/00 ,  H01L23/02 ,  H01L23/13 ,  H01L23/28 ,  H01L23/31 ,  H01L23/34 ,  H01L23/44 ,  H01L23/48 ,  H01L23/488 ,  H01L23/498 ,  H01L23/50 ,  H01L23/52 ,  H01L23/538 ,  H01L23/552 ,  H01L23/66 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/11 ,  H01L25/16 ,  H01L25/18 ,  H05K1/11 ,  H05K3/40

CPC classification number: H01L25/18 ,  H01L21/4846 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/17 ,  H01L24/43 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/89 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H05K1/113 ,  H05K3/4038 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/08238 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48472 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/143 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1511 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/381 ,  Y10T29/49124 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/48472 ,  H01L2224/48227 ,  H01L2924/00

Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

公开(公告)号：US20220344318A1

公开(公告)日：2022-10-27

申请号：US17855664

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Russell K. MORTENSEN ,  Robert M. Nickerson ,  Nicholas R. Watts

IPC: H01L25/18 ,  H01L23/498 ,  H01L23/00 ,  H01L25/10 ,  H05K1/11 ,  H05K3/40 ,  H01L21/48 ,  H01L25/00 ,  H01L25/065

Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

公开(公告)号：US10607976B2

公开(公告)日：2020-03-31

申请号：US15087153

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Russell K. Mortensen ,  Robert M. Nickerson ,  Nicholas R. Watts

IPC: H01L21/50 ,  H01L21/56 ,  H01L21/58 ,  H01L21/60 ,  H01L23/02 ,  H01L23/34 ,  H01L23/44 ,  H01L23/48 ,  H01L23/538 ,  H01L25/18 ,  H01L23/498 ,  H01L23/00 ,  H01L25/10 ,  H05K1/11 ,  H05K3/40 ,  H01L21/48 ,  H01L25/00 ,  H01L25/065

Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

公开(公告)号：US10121722B1

公开(公告)日：2018-11-06

申请号：US15721880

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Chandra M. Jha ,  Eric J. Li ,  Zhaozhi Li ,  Robert M. Nickerson

IPC: H01L23/34 ,  H01L23/373 ,  H01L23/00

Abstract: A device package and a method of forming the device package are described. The device package has a package layer disposed on a substrate. The package layer includes a mold layer surrounding solder balls and a die. The device package also has a trench disposed in the mold layer to surround the die of the package layer. The device package further includes a conductive layer disposed on a top surface of the die. The conductive layer is disposed over the top surface of the die and in the trench of the package layer. The trench may have a specified distance between the die edges, and a specified width and a specified depth based on the conductive layer. The device package may include an interposer with solder balls disposed on the conductive layer and above the package layer, and an underfill layer disposed between the interposer and the package layer.

公开(公告)号：US09613934B2

公开(公告)日：2017-04-04

申请号：US14621936

申请日：2015-02-13

Applicant: INTEL CORPORATION

Inventor： Sandeep Razdan ,  Edward R. Prack ,  Sairam Agraharam ,  Robert L. Sankman ,  Shan Zhong ,  Robert M. Nickerson

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/10 ,  C09J9/02 ,  H01L23/498 ,  H01L21/56 ,  H01L23/528 ,  H01L23/532 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  C09J9/02 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49866 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/5329 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/95 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/13005 ,  H01L2224/13025 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29078 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/2939 ,  H01L2224/29411 ,  H01L2224/29439 ,  H01L2224/29444 ,  H01L2224/29447 ,  H01L2224/29455 ,  H01L2224/29499 ,  H01L2224/73104 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83851 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13613 ,  H01L2924/014 ,  H01L2924/207 ,  H01L2924/0665 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit (IC) package assemblies. In one embodiment, an apparatus includes a first die having a plurality of transistor devices disposed on an active side of the first die and a plurality of interconnect structures electrically coupled with the first die, wherein individual interconnect structures of the plurality of interconnect structures have a polymer core, and an electrically conductive material disposed on the polymer core, the electrically conductive material being configured to route electrical signals between the transistor devices of the first die and a second die. Other embodiments may be described and/or claimed.

公开(公告)号：US20150162313A1

公开(公告)日：2015-06-11

申请号：US14621936

申请日：2015-02-13

Applicant: INTEL CORPORATION

Inventor： Sandeep Razdan ,  Edward R. Prack ,  Sairam Agraharam ,  Robert L. Sankman ,  Shan Zhong ,  Robert M. Nickerson

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/528 ,  H01L23/532 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0657 ,  C09J9/02 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49866 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/5329 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/95 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/13005 ,  H01L2224/13025 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29078 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/2939 ,  H01L2224/29411 ,  H01L2224/29439 ,  H01L2224/29444 ,  H01L2224/29447 ,  H01L2224/29455 ,  H01L2224/29499 ,  H01L2224/73104 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83851 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13613 ,  H01L2924/014 ,  H01L2924/207 ,  H01L2924/0665 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit (IC) package assemblies. In one embodiment, an apparatus includes a first die having a plurality of transistor devices disposed on an active side of the first die and a plurality of interconnect structures electrically coupled with the first die, wherein individual interconnect structures of the plurality of interconnect structures have a polymer core, and an electrically conductive material disposed on the polymer core, the electrically conductive material being configured to route electrical signals between the transistor devices of the first die and a second die. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及在集成电路（IC）封装组件中具有聚合物芯的互连结构的技术和配置。 在一个实施例中，一种装置包括具有设置在第一管芯的有源侧上的多个晶体管器件的第一管芯和与第一管芯电耦合的多个互连结构，其中多个互连结构中的各个互连结构具有 聚合物芯和设置在聚合物芯上的导电材料，所述导电材料被配置为在第一管芯的晶体管器件和第二管芯之间布置电信号。 可以描述和/或要求保护其他实施例。