公开(公告)号：US20220196914A1

公开(公告)日：2022-06-23

申请号：US17131678

申请日：2020-12-22

申请人： Intel Corporation

发明人： Jeremy D. ECTON ,  Hiroki TANAKA ,  Brandon C. MARIN ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Bai NIE ,  Haobo CHEN ,  Zhichao ZHANG ,  Sai VADLAMANI ,  Aleksandar ALEKSOV

IPC分类号： G02B6/12 ,  H01L23/48 ,  G02B6/02 ,  H01L25/065

摘要： Embodiments disclosed herein include electronic packages and methods of forming such structures. In an embodiment, an electronic package comprises a package substrate, a first die over the package substrate, and a second die over the package substrate. In an embodiment, the electronic package further comprises an optical waveguide on the package substrate. In an embodiment, a first end of the optical waveguide is below the first die and a second end of the optical waveguide is below the second die. In an embodiment, the optical waveguide communicatively couples the first die to the second die.

公开(公告)号：US20220085143A1

公开(公告)日：2022-03-17

申请号：US17023249

申请日：2020-09-16

申请人： Intel Corporation

发明人： Beomseok CHOI ,  Huong DO ,  Sai VADLAMANI

IPC分类号： H01L49/02 ,  H01F27/28 ,  H01F27/32 ,  H01F27/245 ,  H01L23/31

摘要： Embodiments disclosed herein include magnetic structures and methods of forming such structures. In an embodiment, the magnetic structure includes an interconnect. In an embodiment, the interconnect comprises a core, where the core has a thickness and a length between a first end and a second end. In an embodiment, the core is conductive. In an embodiment, the interconnect further comprises a magnetic sheet surrounding the core. In an embodiment, the magnetic sheet comprises is a magnetic layer with a microstructure that comprises grains that are substantially aligned in a single direction.

公开(公告)号：US20200006211A1

公开(公告)日：2020-01-02

申请号：US16019996

申请日：2018-06-27

申请人： INTEL CORPORATION

发明人： Andrew J. BROWN ,  Lauren A. LINK ,  Sai VADLAMANI ,  Prithwish CHATTERJEE ,  Lisa CHEN

IPC分类号： H01L23/498 ,  H01L23/14 ,  H01L23/15 ,  H05K1/18 ,  H05K1/03 ,  D06M11/81 ,  D06B3/10 ,  D03D1/00 ,  D03D15/00 ,  B32B5/26 ,  B32B5/02 ,  B32B7/12

摘要： Apparatuses, systems and methods associated with substrate assemblies for computer devices are disclosed herein. In embodiments, a core for a substrate assembly includes a first metal region, a second metal region, and a dielectric region located between the first metal region and the second metal region. The dielectric region includes one or more fibers, wherein each of the one or more fibers includes aluminum, boron, silicon, or oxide. Other embodiments may be described and/or claimed.

公开(公告)号：US20240021522A1

公开(公告)日：2024-01-18

申请号：US18253945

申请日：2020-12-23

申请人： Intel Corporation

发明人： Tolga ACIKALIN ,  Tae Young YANG ,  Debabani CHOUDHURY ,  Shuhei YAMADA ,  Roya DOOSTNEJAD ,  Hosein NIKOPOUR ,  Issy KIPNIS ,  Oner ORHAN ,  Mehnaz RAHMAN ,  Kenneth P. FOUST ,  Christopher D. HULL ,  Telesphor KAMGAING ,  Omkar KARHADE ,  Stefano PELLERANO ,  Peter SAGAZIO ,  Sai VADLAMANI

IPC分类号： H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L23/66 ,  H01L23/498 ,  H01Q1/22

CPC分类号： H01L23/5381 ,  H01L25/0652 ,  H01L24/16 ,  H01L23/66 ,  H01L23/49822 ,  H01Q1/2283 ,  H01L24/81 ,  H01L2924/14222 ,  H01L2924/1431 ,  H01L2223/6677 ,  H01L2223/6616 ,  H01L2223/6655 ,  H01L2224/16235 ,  H01L2224/16146

摘要： Various devices, systems, and/or methods perform wireless chip to chip high speed data transmission. Strategies for such transmission include use of improved microbump antennas, wireless chip to chip interconnects, precoding and decoding strategies, channel design to achieve spatial multiplexing gain in line of sight transmissions, open cavity chip design for improved transmission, and/or mixed signal channel equalization.

公开(公告)号：US20230245940A1

公开(公告)日：2023-08-03

申请号：US18133868

申请日：2023-04-12

申请人： Intel Corporation

发明人： Rahul JAIN ,  Kyu Oh LEE ,  Siddharth K. ALUR ,  Wei-Lun K. JEN ,  Vipul V. MEHTA ,  Ashish DHALL ,  Sri Chaitra J. CHAVALI ,  Rahul N. MANEPALLI ,  Amruthavalli P. ALUR ,  Sai VADLAMANI

IPC分类号： H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L23/532 ,  H01L23/498

CPC分类号： H01L23/3185 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0655 ,  H01L23/53295 ,  H01L23/3128 ,  H01L24/06 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/16227 ,  H01L2924/18161 ,  H01L2224/83051 ,  H01L2224/81

摘要： An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.

公开(公告)号：US20230101340A1

公开(公告)日：2023-03-30

申请号：US17485295

申请日：2021-09-24

申请人： Intel Corporation

发明人： Kaveh HOSSEINI ,  Omkar KARHADE ,  Ravindranath V. MAHAJAN ,  Sergey Yuryevich SHUMARAYEV ,  Yew F. KOK ,  Sai VADLAMANI

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00

摘要： Embodiments disclosed herein include electronic packages and methods of assembling an electronic package. In an embodiment, an electronic package comprises a package substrate with a stepped top surface, and a first die on a first plateau of the stepped top surface. In an embodiment, a second die is on a second plateau of the stepped top surface, where the second die extends over the first die, In an embodiment, a third die is on a third plateau of the stepped top surface, where the third die extends over the second die.

公开(公告)号：US20220413240A1

公开(公告)日：2022-12-29

申请号：US17357941

申请日：2021-06-24

申请人： Intel Corporation

发明人： Srikant NEKKANTY ,  Pooya TADAYON ,  Wesley MORGAN ,  Tarek A. IBRAHIM ,  Sai VADLAMANI

IPC分类号： G02B6/42

摘要： Embodiments described herein may be related to apparatuses, processes, and techniques related to a cavity created in a package substrate, where the surface of the substrate at the bottom of the cavity, or alignment features at the surface of the substrate at the bottom of the cavity are used to accurately align a lens of a FAU to a lens of a PIC. In embodiments, the surface of the substrate at the bottom of the cavity has additional standoff pedestal features to aid in height tolerance control of the FAU to properly align the FAU lens when attached. Other embodiments may be described and/or claimed.

公开(公告)号：US20220359115A1

公开(公告)日：2022-11-10

申请号：US17873509

申请日：2022-07-26

申请人： Intel Corporation

发明人： Kyu-Oh LEE ,  Rahul JAIN ,  Sai VADLAMANI ,  Cheng XU ,  Ji Yong PARK ,  Junnan ZHAO ,  Seo Young KIM

IPC分类号： H01F27/32 ,  H01L23/498 ,  H01F41/04 ,  H01L21/48 ,  H01F27/28

摘要： Apparatuses, systems and methods associated with a substrate assembly with an encapsulated magnetic feature for an inductor are disclosed herein. In embodiments, a substrate assembly may include a base substrate, a magnetic feature encapsulated within the base substrate, and a coil, wherein a portion of the coil extends through the magnetic feature. Other embodiments may be described and/or claimed.

公开(公告)号：US20190304933A1

公开(公告)日：2019-10-03

申请号：US15938114

申请日：2018-03-28

申请人： Intel Corporation

发明人： Cheng XU ,  Kyu-Oh LEE ,  Junnan ZHAO ,  Rahul JAIN ,  Ji Yong PARK ,  Sai VADLAMANI ,  Seo Young KIM

IPC分类号： H01L23/64 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

摘要： Embodiments include an electronic package that includes a first layer that comprises a dielectric material and a second layer over the first layer, where the second layer comprises a magnetic material. In an embodiment, a third layer is formed over the second layer, where the third layer comprises a dielectric material. In an embodiment, the third layer entirely covers a first surface of the second layer. In an embodiment a first conductive layer and a second conductive layer are embedded within the second layer. In an embodiment, sidewalls of the first conductive layer and the second conductive layer are substantially vertical.