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    Set technique for phase change memory
    13.
    发明授权
    Set technique for phase change memory 有权

    公开(公告)号：US10884640B2

    公开(公告)日：2021-01-05

    申请号：US16373282

    申请日：2019-04-02

    Applicant: Intel Corporation

    Inventor： Koushik Banerjee ,  Lu Liu ,  Sanjay Rangan ,  Enrico Varesi ,  Innocenzo Tortorelli ,  Hongmei Wang ,  Mattia Boniardi

    IPC: G06F12/00 ,  G06F3/06 ,  G11C13/00 ,  G06F12/02

    Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.

    Tailoring current magnitude and duration during a programming pulse for a memory device
    14.
    发明授权
    Tailoring current magnitude and duration during a programming pulse for a memory device 有权

    公开(公告)号：US10796761B2

    公开(公告)日：2020-10-06

    申请号：US16520213

    申请日：2019-07-23

    Applicant: Intel Corporation

    Inventor： Koushik Banerjee ,  Lu Liu ,  Sanjay Rangan

    IPC: G11C16/04 ,  G11C13/00

    Abstract: Technology for a memory device is described. The memory device can include an array of memory cells and a memory controller. The memory controller can receive a request to program a memory cell within the array of memory cells. The memory controller can select a current magnitude and a duration of the current magnitude for a programming set pulse based on a polarity of access for the memory cell, a number of prior write cycles for the memory cell, and electrical distances between the memory cell and wordline/bitline decoders within the array of memory cells. The memory controller can initiate, in response to the request, the programming set pulse to program the memory cell within the array of memory cells. The selected current magnitude and the selected duration of the current magnitude can be applied during the programming set pulse.

    Multistage set procedure for phase change memory
    15.
    发明授权
    Multistage set procedure for phase change memory 有权

    公开(公告)号：US10446229B2

    公开(公告)日：2019-10-15

    申请号：US15894822

    申请日：2018-02-12

    Applicant: Intel Corporation

    Inventor： Sanjay Rangan ,  Kiran Pangal ,  Nevil N Gajera ,  Lu Liu ,  Gayathri Rao Subbu

    IPC: G11C11/16 ,  G11C13/00 ,  G11C7/04 ,  H01L45/00

    Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.

    SET TECHNIQUE FOR PHASE CHANGE MEMORY
    16.
    发明申请
    SET TECHNIQUE FOR PHASE CHANGE MEMORY 审中-公开

    公开(公告)号：US20190102099A1

    公开(公告)日：2019-04-04

    申请号：US15721388

    申请日：2017-09-29

    Applicant: INTEL CORPORATION

    Inventor： Koushik Banerjee ,  Lu Liu ,  Sanjay Rangan ,  Enrico Varesi ,  Innocenzo Tortorelli ,  Hongmei Wang ,  Mattia Boniardi

    IPC: G06F3/06 ,  G11C13/00

    Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.

    Multi-level cell (MLC) techniques and circuits for cross-point memory
    19.
    发明授权
    Multi-level cell (MLC) techniques and circuits for cross-point memory 有权

    公开(公告)号：US10957387B1

    公开(公告)日：2021-03-23

    申请号：US16687468

    申请日：2019-11-18

    Applicant: Intel Corporation

    Inventor： Davide Mantegazza ,  Kiran Pangal ,  Sanjay Rangan

    IPC: G11C11/00 ,  G11C11/56 ,  G11C13/00 ,  H01L45/00 ,  H01L27/24

    Abstract: Techniques for accessing multi-level cell (MLC) crosspoint memory cells are described. In one example, a circuit includes a crosspoint memory cell that can be in one of multiple resistive states (e.g., four or more resistive states). In one example, to perform a read, circuitry coupled with the memory cell applies one or more sub-reads at different read voltages. For example, the circuitry applies a first read voltage and detects if the memory cell thresholds in response to the first read voltage. If the memory cell thresholded in response to the first read voltage, the state of the memory cell can be determined without further reads. If the memory cell did not threshold in response to the first read voltage, a second read voltage with a greater magnitude is applied across the memory cell. If the memory cell thresholded in response to the second read voltage, the state of the memory cell can be determined without further reads. If the memory cell did not threshold in response to the first read voltage, a third read voltage with a greater magnitude is applied across the memory cell. In one example, the thresholding of the memory cell triggers the application of a write current to write back the state of the bit due to read disturb from the read.

    Multistage set procedure for phase change memory
    20.
    发明授权
    Multistage set procedure for phase change memory 有权

    公开(公告)号：US10783966B2

    公开(公告)日：2020-09-22

    申请号：US16593530

    申请日：2019-10-04

    Applicant: Intel Corporation

    Inventor： Sanjay Rangan ,  Kiran Pangal ,  Nevil N Gajera ,  Lu Liu ,  Gayathri Rao Subbu

    IPC: G11C11/16 ,  G11C13/00 ,  G11C7/04 ,  H01L45/00

    Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.

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