公开(公告)号：US20160358716A1

公开(公告)日：2016-12-08

申请号：US15239285

申请日：2016-08-17

Applicant: Intel Corporation

Inventor： Donald S. Gardner ,  Cary L. Pint ,  Scott B. Clendenning

IPC: H01G11/02 ,  H01G11/84 ,  H01G11/30 ,  H01G11/54 ,  H01G11/52 ,  H01G11/26

CPC classification number: H01G11/02 ,  G06F1/1635 ,  H01G9/04 ,  H01G11/26 ,  H01G11/30 ,  H01G11/46 ,  H01G11/52 ,  H01G11/54 ,  H01G11/84 ,  H04M1/0262 ,  H04M2001/0204 ,  Y02E60/13 ,  Y10T29/49115

Abstract: An energy storage device comprises a first porous semiconducting structure (510) comprising a first plurality of channels (511) that contain a first electrolyte (514) and a second porous semiconducting structure (520) comprising a second plurality of channels (521) that contain a second electrolyte (524). In one embodiment, the energy storage device further comprises a film (535) on at least one of the first and second porous semiconducting structures, the film comprising a material capable of exhibiting reversible electron transfer reactions. In another embodiment, at least one of the first and second electrolytes contains a plurality of metal ions. In another embodiment, the first and second electrolytes, taken together, comprise a redox system.

Abstract translation: 能量存储装置包括第一多孔半导体结构（510），第一多孔半导体结构（510）包括含有第一电解质（514）的第一多个通道（511）和包含第二多个通道（521）的第二多孔半导体结构（520） 第二电解质（524）。 在一个实施例中，能量存储装置还包括在第一和第二多孔半导体结构中的至少一个上的膜（535），该膜包括能够显示可逆电子转移反应的材料。 在另一个实施方案中，第一和第二电解质中的至少一个包含多个金属离子。 在另一个实施方案中，第一和第二电解质一起组成氧化还原体系。

公开(公告)号：US20250157808A1

公开(公告)日：2025-05-15

申请号：US18506838

申请日：2023-11-10

Applicant: Intel Corporation

Inventor： Charles Mokhtarzadeh ,  Scott Semproni ,  Scott B. Clendenning

IPC: H01L21/02 ,  G03C1/08

Abstract: Methods and apparatus utilizing indium-based precursors in semiconductor manufacturing are disclosed. An example apparatus includes a substrate layer, the substrate layer to be included an integrated circuit package, and a photoresist on the substrate layer, the photoresist including indium.

公开(公告)号：US20250006840A1

公开(公告)日：2025-01-02

申请号：US18344022

申请日：2023-06-29

Applicant: INTEL CORPORATION

Inventor： Rachel A. Steinhardt ,  Kevin P. O'Brien ,  Dmitri Evgenievich Nikonov ,  John J. Plombon ,  Tristan A. Tronic ,  Ian Alexander Young ,  Matthew V. Metz ,  Marko Radosavljevic ,  Carly Rogan ,  Brandon Holybee ,  Raseong Kim ,  Punyashloka Debashis ,  Dominique A. Adams ,  I-Cheng Tung ,  Arnab Sen Gupta ,  Gauri Auluck ,  Scott B. Clendenning ,  Pratyush P. Buragohain ,  Hai Li

IPC: H01L29/78 ,  H01L29/76 ,  H01L29/786

Abstract: In one embodiment, a negative capacitance transistor device includes a perovskite semiconductor material layer with first and second perovskite conductors on opposite ends of the perovskite semiconductor material layer. The device further includes a dielectric material layer on the perovskite semiconductor material layer between the first and second perovskite conductors, a perovskite ferroelectric material layer on the dielectric material layer, and a third perovskite conductor on the perovskite ferroelectric material layer.

公开(公告)号：US20250006791A1

公开(公告)日：2025-01-02

申请号：US18346227

申请日：2023-07-01

Applicant: Intel Corporation

Inventor： Rachel A. Steinhardt ,  Kevin P. O'Brien ,  Dominique A. Adams ,  Gauri Auluck ,  Pratyush P. Buragohain ,  Scott B. Clendenning ,  Punyashloka Debashis ,  Arnab Sen Gupta ,  Brandon Holybee ,  Raseong Kim ,  Matthew V. Metz ,  John J. Plombon ,  Marko Radosavljevic ,  Carly Rogan ,  Tristan A. Tronic ,  I-Cheng Tung ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/12 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: Perovskite oxide field effect transistors comprise perovskite oxide materials for the channel, source, drain, and gate oxide regions. The source and drain regions are doped with a higher concentration of n-type or p-type dopants (depending on whether the transistor is an n-type or p-type transistor) than the dopant concentration in the channel region to minimize Schottky barrier height between the source and drain regions and the source and drain metal contact and contact resistance.

公开(公告)号：US20240210821A1

公开(公告)日：2024-06-27

申请号：US18145038

申请日：2022-12-22

Applicant: Intel Corporation

Inventor： Charles Cameron Mokhtarzadeh ,  James Blackwell ,  Scott Semproni ,  Scott B. Clendenning ,  Lauren Elizabeth Doyle

IPC: G03F7/00 ,  G03F7/038 ,  G03F7/16 ,  G03F7/20 ,  G03F7/40

CPC classification number: G03F7/0032 ,  G03F7/038 ,  G03F7/162 ,  G03F7/167 ,  G03F7/2004 ,  G03F7/40

Abstract: Precursors and methods related to a bismuth oxy-carbide-based photoresist are disclosed herein. In some embodiments, a method for forming a bismuth oxy-carbide-based photoresist may include exposing a bismuth-containing precursor and a co-reagent to a substrate to form a bismuth oxy-carbide-based photoresist having a formula BixOyCz on the substrate, where x is 1 or 2, y is between 2 and 4, and z is between 1 and 5, the bismuth-containing precursor having a formula R′Bi(NR2)2 or R′2BiNR2 where R includes methyl, ethyl, isopropyl, tert-butyl, or trimethylsilyl, or NR2 is piperidine, and R′ includes methyl, ethyl, isopropyl, tert-butyl, cyclo-pentyl, cyclo-hexyl, methyl trimethylsilyl, methyl 2-butyl, benzyl, 1-methyl 2-dimethyl propyl, or cyclopentadienyl. In some embodiments, the co-reagent includes water, hydrogen peroxide, oxygen, ozone, formic acid, maleic acid, or an alcohol.

公开(公告)号：US20240105810A1

公开(公告)日：2024-03-28

申请号：US17952161

申请日：2022-09-23

Applicant: Intel Corporation

Inventor： Rachel A. Steinhardt ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Marko Radosavljevic ,  Matthew V. Metz ,  John J. Plombon ,  Raseong Kim ,  Kevin P. O'Brien ,  Scott B. Clendenning ,  Tristan A. Tronic ,  Dominique A. Adams ,  Carly Rogan ,  Arnab Sen Gupta ,  Brandon Holybee ,  Punyashloka Debashis ,  I-Cheng Tung ,  Gauri Auluck

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/516 ,  H01L29/6684 ,  H01L29/66969 ,  H01L29/7831

Abstract: In one embodiment, transistor device includes a first source or drain material on a substrate, a semiconductor material on the first source or drain material, a second source or drain material on the semiconductor material, a dielectric layer on the substrate and adjacent the first source or drain material, a ferroelectric (FE) material on the dielectric layer and adjacent the semiconductor material, and a gate material on or adjacent to the FE material. The FE material may be a perovskite material and may have a lattice parameter that is less than a lattice parameter of the semiconductor material.

公开(公告)号：US20230253444A1

公开(公告)日：2023-08-10

申请号：US17666745

申请日：2022-02-08

Applicant: Intel Corporation

Inventor： Arnab Sen Gupta ,  Kaan Oguz ,  Chia-Ching Lin ,  I-Cheng Tung ,  Sudarat Lee ,  Sou-Chi Chang ,  Matthew V. Metz ,  Scott B. Clendenning ,  Uygar E. Avci ,  Ian A. Young ,  Jason C. Retasket ,  Edward O. Johnson, JR.

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/65 ,  H01L28/75 ,  H01L27/10829

Abstract: Described herein are capacitor devices formed using perovskite insulators. In one example, a perovskite templating material is formed over an electrode, and a perovskite insulator layer is grown over the templating material. The templating material improves the crystal structure and electrical properties in the perovskite insulator layer. One or both electrodes may be ruthenium. In another example, a perovskite insulator layer is formed between two layers of indium tin oxide (ITO), with the ITO layers forming the capacitor electrodes.

公开(公告)号：US11672133B2

公开(公告)日：2023-06-06

申请号：US16447603

申请日：2019-06-20

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Patrick R. Morrow ,  Hui Jae Yoo ,  Sean T. Ma ,  Scott B. Clendenning ,  Abhishek A. Sharma ,  Ehren Mannebach ,  Urusa Alaan

IPC: H10B63/00 ,  H01L21/311 ,  H01L21/768 ,  H10B41/27 ,  H10B43/27

CPC classification number: H10B63/845 ,  H01L21/31116 ,  H01L21/7682 ,  H10B41/27 ,  H10B43/27

Abstract: A memory structure includes conductive lines extending horizontally in a spaced apart fashion within a vertical stack above a base or substrate. The vertical stack includes a plurality of conductive lines, the first and second conductive lines being part of the plurality. A gate structure extends vertically through the first and second conductive lines. The gate structure includes a body of semiconductor material and a dielectric, where the dielectric is between the body and the conductive lines. An isolation material is on at least one side of the vertical stack and in contact with the conductive lines. The vertical stack defines a void located vertically between at the first and second conductive lines in the vertical stack and laterally between the gate structure and the isolation material. The void may extend along a substantial length (e.g., 20 nm or more) of the first and second conductive lines.

公开(公告)号：US11264449B2

公开(公告)日：2022-03-01

申请号：US16828497

申请日：2020-03-24

Applicant: Intel Corporation

Inventor： Sudipto Naskar ,  Manish Chandhok ,  Abhishek A. Sharma ,  Roman Caudillo ,  Scott B. Clendenning ,  Cheyun Lin

IPC: H01L21/00 ,  H01L49/02 ,  H01L27/108

Abstract: Embodiments herein describe techniques for a semiconductor device including a three dimensional capacitor. The three dimensional capacitor includes a pole, and one or more capacitor units stacked around the pole. A capacitor unit of the one or more capacitor units includes a first electrode surrounding and coupled to the pole, a dielectric layer surrounding the first electrode, and a second electrode surrounding the dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20220059668A1

公开(公告)日：2022-02-24

申请号：US16999471

申请日：2020-08-21

Applicant: Intel Corporation

Inventor： Charles Cameron Mokhtarzadeh ,  Sudarat Lee ,  Scott B. Clendenning

IPC: H01L29/49 ,  H01L29/06 ,  H01L29/423 ,  H01L29/51 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  C23C16/06 ,  C23C16/455

Abstract: Disclosed herein are rare-earth materials, structures, and methods for integrated circuit (IC) structures. For example, in some embodiments, a precursor for atomic layer deposition (ALD) of a rare-earth material in an IC structure may include a rare-earth element and a pincer ligand bonded to the rare-earth element.