公开(公告)号：US20180124685A1

公开(公告)日：2018-05-03

申请号：US15567473

申请日：2015-12-01

Applicant: INTEL CORPORATION

Inventor： Satish Jha ,  Mohammad Mamunur Rashid ,  Rath Vannithamby ,  Tao Wu

IPC: H04W48/10 ,  H04W68/02 ,  H04W4/00

Abstract: Technology for a user equipment (UE) operable to receive system information change notifications from an eNodeB is disclosed. The UE can receive one or more system information (SI) change notifications that indicate a change has occurred in one or more system information blocks (SIBs). The UE can receive a SIB1 that is associated with a value tag, and the SIB1 can include a bit-map that indicates which of the one or more SIBs include a change. The UE can compare the value tag associated with the SIB1 with a value tag stored at the UE. The UE can obtain scheduling information for the one or more SIBs that include a change according to the bitmap when the value tag associated with the SIB1 does not equal to the value tag stored at the UE. The UE can retrieve the SIBs that include a change using the scheduling information.

公开(公告)号：US20170250150A1

公开(公告)日：2017-08-31

申请号：US15596968

申请日：2017-05-16

Applicant: Intel Corporation

Inventor： Manohar S. KONCHADY ,  Tao Wu ,  Mihir K. Roy ,  Wei-Lun K. Jen ,  Yi Li

IPC: H01L21/71 ,  H01L23/52 ,  H01L23/02

CPC classification number: H01L21/6835 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5389 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/73267 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19106

Abstract: A coreless package substrate with dual side solder resist layers is disclosed. The coreless package substrate has a top side and a bottom side opposite of the top side and includes a single build-up structure formed of at least one insulating layer, at least one via, and at least one conductive layer. The coreless package substrate also includes a bottom plurality of contact pads on the bottom side, and a top plurality of contact pads on the top side. A bottom solder resist layer is on the bottom side, and a top solder resist layer is on the top side. The concept of dual side solder resist is extended to packages with interconnect bridge with C4 interconnection pitch over a wide range.

公开(公告)号：US20160300803A1

公开(公告)日：2016-10-13

申请号：US15187737

申请日：2016-06-20

Applicant: Intel Corporation

Inventor： Zhichao Zhang ,  Tolga Memioglu ,  Tao Wu ,  Kemal Aygun

IPC: H01L23/66 ,  H01L23/498 ,  H01P3/08 ,  H01L23/50 ,  H01L25/18 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/66 ,  H01L21/76877 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5226 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/18 ,  H01L2223/6627 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2924/01029 ,  H01L2924/1426 ,  H01L2924/143 ,  H01L2924/14361 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01P3/081 ,  H05K1/0216 ,  H05K1/0222 ,  H05K1/0228 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Transmission lines with a first dielectric material separating signal traces and a second dielectric material separating the signal traces from a ground plane. In embodiments, mutual capacitance is tuned relative to self-capacitance to reverse polarity of far end crosstalk between a victim and aggressor channel relative to that induced by other interconnect portions along the length of the channels, such as inductively coupled portions. In embodiments, a transmission line for a single-ended channel includes a material of a higher dielectric constant within the same routing plane as a microstrip or stripline conductor, and a material of a lower dielectric constant between the conductor and the ground plane(s). In embodiments, a transmission line for a differential pair includes a material of a lower dielectric constant within the same routing plane as a microstrip or stripline conductors, and a material of a higher dielectric constant between the conductors and the ground plane(s).

Abstract translation: 具有分离信号迹线的第一介电材料的传输线和将信号迹线与接地平面分开的第二介电材料。 在实施例中，互电容相对于自电容被调谐，以相对于沿着诸如电感耦合部分的通道的长度的其它互连部分感应到的远端串扰的极性反转。 在实施例中，用于单端通道的传输线包括在与微带线或带状线导体相同的布线平面内具有较高介电常数的材料，以及在导体和接地平面之间具有较低介电常数的材料， 。 在实施例中，用于差分对的传输线包括在与微带线或带状线导体相同的布线平面内具有较低介电常数的材料，以及在导体和接地平面之间具有较高介电常数的材料。

公开(公告)号：US20160104632A1

公开(公告)日：2016-04-14

申请号：US14974726

申请日：2015-12-18

Applicant: Intel Corporation

Inventor： Zhichao Zhang ,  Tao Wu ,  Zhiguo Qian ,  Kemal Aygun

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/81 ,  H01L2224/16227 ,  H01L2924/1432 ,  H01L2924/14335 ,  H01L2924/1517 ,  H01L2924/15311

Abstract: Some embodiments described herein include apparatuses and methods of forming such apparatuses. One such embodiment may include a routing arrangement having pads to be coupled to a semiconductor die, with a first trace coupled to a first pad among the pads, and a second trace coupled to a second pad among the pads. The first and second traces may have different thicknesses. Other embodiments including additional apparatuses and methods are described.

Abstract translation: 这里描述的一些实施例包括形成这种装置的装置和方法。 一个这样的实施例可以包括具有要耦合到半导体管芯的焊盘的布线布置，其中第一迹线耦合到焊盘之间的第一焊盘，以及耦合到焊盘之间的第二焊盘的第二迹线。 第一和第二迹线可以具有不同的厚度。 描述包括附加装置和方法的其他实施例。

公开(公告)号：US09093313B2

公开(公告)日：2015-07-28

申请号：US14481766

申请日：2014-09-09

Applicant: Intel Corporation

Inventor： Mark S. Hlad ,  Islam A. Salama ,  Mihir K. Roy ,  Tao Wu ,  Yueli Liu ,  Kyu Oh Lee

IPC: H01L21/4763 ,  H01L23/00 ,  H05K1/11 ,  H05K3/10 ,  H05K3/42 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H05K3/34

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/563 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/50 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/1112 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11466 ,  H01L2224/119 ,  H01L2224/13005 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/165 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81444 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01103 ,  H01L2924/01108 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15321 ,  H01L2924/2064 ,  H01L2924/37001 ,  H01L2924/3841 ,  H05K1/113 ,  H05K3/107 ,  H05K3/3436 ,  H05K3/421 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.

Abstract translation: 封装衬底，能够减少凸起间距和封装组件。 表面级金属特征嵌入表面级电介质层中，其表面光洁度从表面电介质的顶表面突出，用于组装而无阻焊，具有焊接连接点的IC芯片。 制造封装衬底以实现多级跟踪路由，每个跟踪路由级别能够减少最小迹线宽度和间距。

公开(公告)号：US20150008578A1

公开(公告)日：2015-01-08

申请号：US14481766

申请日：2014-09-09

Applicant: Intel Corporation

Inventor： Mark S. Hlad ,  Islam A. Salama ,  Mihir K. Roy ,  Tao Wu ,  Yueli Liu ,  Kyu Oh Lee

IPC: H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/563 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/50 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/1112 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11466 ,  H01L2224/119 ,  H01L2224/13005 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/165 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81444 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01103 ,  H01L2924/01108 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15321 ,  H01L2924/2064 ,  H01L2924/37001 ,  H01L2924/3841 ,  H05K1/113 ,  H05K3/107 ,  H05K3/3436 ,  H05K3/421 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.

公开(公告)号：US20180166294A1

公开(公告)日：2018-06-14

申请号：US15377635

申请日：2016-12-13

Applicant: Intel Corporation

Inventor： Zheng Zhou ,  Yi Li ,  Tao Wu ,  Nikhil Sharma

IPC: H01L21/3105 ,  H01L21/683 ,  H01L21/56 ,  H05B3/22

CPC classification number: H05B3/22 ,  H01L21/31058 ,  H01L21/4846 ,  H01L23/498 ,  H01L2021/607 ,  H05B2203/033

Abstract: Embodiments herein relate to methods and apparatus to achieve substantially uniform package thickness after forming a buildup layer on a package substrate of an integrated circuit. Some embodiments include applying a resin to the buildup layer to form a resin layer on top of at least a portion of the buildup layer and substantially evening out the surface formed by the resin layer. Some embodiments include vibrating a hot press onto the top surface of the buildup layer and vibrating the hot press in an ultrasonic and/or a scrubbing motion. Other embodiments may be described and/or claimed.

公开(公告)号：US09955453B2

公开(公告)日：2018-04-24

申请号：US14834963

申请日：2015-08-25

Applicant: Intel Corporation

Inventor： Mohammad Mamunur Rashid ,  Satish Chandra Jha ,  Tao Wu ,  Rath Vannithamby

IPC: H04W4/00 ,  H04W68/02 ,  H04W68/00

CPC classification number: H04W68/02 ,  H04W4/70 ,  H04W68/005

Abstract: Embodiments of an Evolved Node-B (eNB), User Equipment (UE), and methods for paging are disclosed herein. The eNB may transmit a paging message that may include paging identifiers to indicate an intention of the eNB to send downlink data to the first group of UEs. The paging message may further include a bitmap of paging indicators to indicate whether the eNB intends to send downlink data to a second group of UEs. The paging message may include the bitmap when a length of the bitmap is less than a combined length of paging identifiers for a paging portion of second group of UEs to which the eNB intends to send downlink data.

公开(公告)号：US09564407B2

公开(公告)日：2017-02-07

申请号：US15187737

申请日：2016-06-20

Applicant: Intel Corporation

Inventor： Zhichao Zhang ,  Tolga Memioglu ,  Tao Wu ,  Kemal Aygun

IPC: H01L23/48 ,  H05K1/11 ,  H01L23/52 ,  H01L23/66 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L23/50 ,  H01L25/18 ,  H01P3/08 ,  H05K1/02

CPC classification number: H01L23/66 ,  H01L21/76877 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5226 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/18 ,  H01L2223/6627 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2924/01029 ,  H01L2924/1426 ,  H01L2924/143 ,  H01L2924/14361 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01P3/081 ,  H05K1/0216 ,  H05K1/0222 ,  H05K1/0228 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Transmission lines with a first dielectric material separating signal traces and a second dielectric material separating the signal traces from a ground plane. In embodiments, mutual capacitance is tuned relative to self-capacitance to reverse polarity of far end crosstalk between a victim and aggressor channel relative to that induced by other interconnect portions along the length of the channels, such as inductively coupled portions. In embodiments, a transmission line for a single-ended channel includes a material of a higher dielectric constant within the same routing plane as a microstrip or stripline conductor, and a material of a lower dielectric constant between the conductor and the ground plane(s). In embodiments, a transmission line for a differential pair includes a material of a lower dielectric constant within the same routing plane as a microstrip or stripline conductors, and a material of a higher dielectric constant between the conductors and the ground plane(s).

Abstract translation: 具有分离信号迹线的第一介电材料的传输线和将信号迹线与接地平面分开的第二介电材料。 在实施例中，互电容相对于自电容被调谐，以相对于沿着诸如电感耦合部分的通道的长度的其它互连部分感应到的远端串扰的极性反转。 在实施例中，用于单端通道的传输线包括在与微带线或带状线导体相同的布线平面内具有较高介电常数的材料，以及在导体和接地平面之间具有较低介电常数的材料， 。 在实施例中，用于差分对的传输线包括在与微带线或带状线导体相同的布线平面内具有较低介电常数的材料，以及在导体和接地平面之间具有较高介电常数的材料。

公开(公告)号：US09391018B2

公开(公告)日：2016-07-12

申请号：US14171714

申请日：2014-02-03

Applicant: Intel Corporation

Inventor： Zhichao Zhang ,  Tolga Memioglu ,  Tao Wu ,  Kemal Aygun

IPC: H01L21/768 ,  H01L23/522 ,  H01F5/04 ,  H01F27/28 ,  H01L23/498 ,  H01L23/66 ,  H01L23/00

CPC classification number: H01L23/66 ,  H01L21/76877 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5226 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/18 ,  H01L2223/6627 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2924/01029 ,  H01L2924/1426 ,  H01L2924/143 ,  H01L2924/14361 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01P3/081 ,  H05K1/0216 ,  H05K1/0222 ,  H05K1/0228 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Transmission lines with a first dielectric material separating signal traces and a second dielectric material separating the signal traces from a ground plane. In embodiments, mutual capacitance is tuned relative to self-capacitance to reverse polarity of far end crosstalk between a victim and aggressor channel relative to that induced by other interconnect portions along the length of the channels, such as inductively coupled portions. In embodiments, a transmission line for a single-ended channel includes a material of a higher dielectric constant within the same routing plane as a microstrip or stripline conductor, and a material of a lower dielectric constant between the conductor and the ground plane(s). In embodiments, a transmission line for a differential pair includes a material of a lower dielectric constant within the same routing plane as a microstrip or stripline conductors, and a material of a higher dielectric constant between the conductors and the ground plane(s).

Abstract translation: 具有分离信号迹线的第一介电材料的传输线和将信号迹线与接地平面分开的第二介电材料。 在实施例中，互电容相对于自电容被调谐，以相对于沿着诸如电感耦合部分的通道的长度的其它互连部分感应到的远端串扰的极性反转。 在实施例中，用于单端通道的传输线包括在与微带线或带状线导体相同的布线平面内具有较高介电常数的材料，以及在导体和接地平面之间具有较低介电常数的材料， 。 在实施例中，用于差分对的传输线包括在与微带线或带状线导体相同的布线平面内具有较低介电常数的材料，以及在导体和接地平面之间具有较高介电常数的材料。