公开(公告)号：US20220413240A1

公开(公告)日：2022-12-29

申请号：US17357941

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Srikant NEKKANTY ,  Pooya TADAYON ,  Wesley MORGAN ,  Tarek A. IBRAHIM ,  Sai VADLAMANI

IPC: G02B6/42

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to a cavity created in a package substrate, where the surface of the substrate at the bottom of the cavity, or alignment features at the surface of the substrate at the bottom of the cavity are used to accurately align a lens of a FAU to a lens of a PIC. In embodiments, the surface of the substrate at the bottom of the cavity has additional standoff pedestal features to aid in height tolerance control of the FAU to properly align the FAU lens when attached. Other embodiments may be described and/or claimed.

公开(公告)号：US20210090946A1

公开(公告)日：2021-03-25

申请号：US16578698

申请日：2019-09-23

Applicant: Intel Corporation

Inventor： Darko GRUJICIC ,  Matthew ANDERSON ,  Adrian BAYRAKTAROGLU ,  Roy DITTLER ,  Benjamin DUONG ,  Tarek A. IBRAHIM ,  Rahul N. MANEPALLI ,  Suddhasattwa NAD ,  Rengarajan SHANMUGAM ,  Marcel WALL

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Embodiments herein relate to systems, apparatuses, and/or processes directed to a package or a manufacturing process flow for creating a package that uses multiple seeding techniques to fill vias in the package. Embodiments include a first layer of copper seeding coupled with a portion of the boundary surface and a second layer of copper seeding coupled with the boundary surface or the first layer of copper seeding, where the first layer of copper seeding and the second layer of copper seeding have a combined thickness along the boundary surface that is greater than a threshold value.

公开(公告)号：US20250107112A1

公开(公告)日：2025-03-27

申请号：US18371294

申请日：2023-09-21

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Srinivas PIETAMBARAM ,  Mohammad Mamunur RAHMAN ,  Sashi Shekhar KANDANUR ,  Aleksandar ALEKSOV ,  Tarek A. IBRAHIM ,  Rahul N. MANEPALLI

IPC: H01L23/48 ,  H01L23/498

Abstract: Coaxial magnetic inductor structures useful for semiconductor packaging applications are provided. The coaxial magnetic inductors can be located in semiconductor package cores and the semiconductor package cores can be, for example, comprised of an amorphous solid glass material. Methods of manufacturing a coaxial magnetic inductors in a package substrate core are also provided.

公开(公告)号：US20250070030A1

公开(公告)日：2025-02-27

申请号：US18943420

申请日：2024-11-11

Applicant: Intel Corporation

Inventor： Sanka GANESAN ,  Ram VISWANATH ,  Xavier Francois BRUN ,  Tarek A. IBRAHIM ,  Jason M. GAMBA ,  Manish DUBEY ,  Robert Alan MAY

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.

公开(公告)号：US20240217216A1

公开(公告)日：2024-07-04

申请号：US18091028

申请日：2022-12-29

Applicant: INTEL CORPORATION

Inventor： Kristof DARMAWIKARTA ,  Tarek A. IBRAHIM ,  Srinivas V. PIETAMBARAM ,  Dilan SENEVIRATNE ,  Jieying KONG ,  Thomas HEATON ,  Whitney BRYKS ,  Vinith BEJUGAM ,  Junxin WANG ,  Gang DUAN

IPC: B32B17/10 ,  B32B7/12 ,  B32B17/02 ,  B65D85/48

CPC classification number: B32B17/10642 ,  B32B7/12 ,  B32B17/02 ,  B65D85/48 ,  B32B2260/04 ,  B32B2307/202 ,  B32B2457/00

Abstract: Embodiments disclosed herein include package substrates with glass stiffeners. In an embodiment, the package substrate comprises a first layer, where the first layer comprises glass. In an embodiment, the package substrate comprises a second layer over the first layer, where the second layer is a buildup film. In an embodiment, the package substrate further comprises an electrically conductive interconnect structure through the first layer and the second layer.

公开(公告)号：US20240213156A1

公开(公告)日：2024-06-27

申请号：US18089491

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Kristof DARMAWIKARTA ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Tarek A. IBRAHIM ,  Aaron GARELICK ,  Srikant NEKKANTY ,  Ravindranath V. MAHAJAN ,  Rahul N. MANEPALLI

IPC: H01L23/532 ,  H01L23/00 ,  H01L23/15 ,  H01L23/498 ,  H01L23/522 ,  H01L23/535 ,  H01L23/64 ,  H01L25/065

CPC classification number: H01L23/53209 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/5226 ,  H01L23/535 ,  H01L23/642 ,  H01L24/05 ,  H01L24/29 ,  H01L25/0655 ,  H01L2224/04026 ,  H01L2224/05567 ,  H01L2224/29007 ,  H01L2224/29021 ,  H01L2224/29101 ,  H01L2924/1436 ,  H01L2924/15321

Abstract: Embodiments disclosed herein include package substrates. In an embodiment, the package substrate comprises a core and buildup layers over the core. In an embodiment, a pad is provided on the buildup layers. In an embodiment, a liquid metal well is over the pad.

公开(公告)号：US20240006297A1

公开(公告)日：2024-01-04

申请号：US17853582

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Suddhasattwa NAD ,  Kristof DARMAWIKARTA ,  Srinivas V. PIETAMBARAM ,  Tarek A. IBRAHIM ,  Rahul N. MANEPALLI ,  Darko GRUJICIC ,  Marcel WALL ,  Yi YANG

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/49894 ,  H01L21/4846 ,  H01L23/538 ,  H01L21/481

Abstract: Embodiments herein relate to systems, apparatuses, or processes for forming a silicide and a silicon nitrate layer between a copper feature and dielectric to reduce delamination of the dielectric. Embodiments allow an unroughened surface for the copper feature to reduce the insertion loss for transmission lines that go through the unroughened surface of the copper. Embodiments may include sequential interlayers between a dielectric and copper. Other embodiments may be described and/or claimed.

公开(公告)号：US20230343723A1

公开(公告)日：2023-10-26

申请号：US18216005

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Nicholas NEAL ,  Nicholas S. HAEHN ,  Sergio CHAN ARGUEDAS ,  Edvin CETEGEN ,  Jacob VEHONSKY ,  Steve S. CHO ,  Rahul JAIN ,  Antariksh Rao Pratap SINGH ,  Tarek A. IBRAHIM ,  Thomas HEATON

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/367

CPC classification number: H01L23/562 ,  H01L23/5381 ,  H01L23/3675

Abstract: Embodiments disclosed herein include electronic packages with thermal solutions. In an embodiment, an electronic package comprises a package substrate, a first die electrically coupled to the package substrate, and an integrated heat spreader (IHS) that is thermally coupled to a surface of the first die. In an embodiment, the IHS comprises a main body having an outer perimeter, and one or more legs attached to the outer perimeter of the main body, wherein the one or more legs are supported by the package substrate. In an embodiment, the electronic package further comprises a thermal block between the package substrate and the main body of the IHS, wherein the thermal block is within the outer perimeter of the main body.

公开(公告)号：US20230093438A1

公开(公告)日：2023-03-23

申请号：US17481266

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Benjamin DUONG ,  Kristof DARMAWIKARTA ,  Srinivas V. PIETAMBARAM ,  Darko GRUJICIC ,  Bai NIE ,  Tarek A. IBRAHIM ,  Ankur AGRAWAL ,  Sandeep GAAN ,  Ravindranath V. MAHAJAN ,  Aleksandar ALEKSOV

IPC: G02B6/12 ,  H04B10/70 ,  G02B6/124 ,  G02B6/13

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a first layer, where the first layer comprises glass. In an embodiment, a second layer is over the first layer, where the second layer comprises a mold material. In an embodiment, a first photonics integrated circuit (PIC) is within the second layer. In an embodiment, a second PIC is within the second layer, and a waveguide is in the first layer. In an embodiment, the waveguide optically couples the first PIC to the second PIC.

公开(公告)号：US20230083222A1

公开(公告)日：2023-03-16

申请号：US17476357

申请日：2021-09-15

Applicant: Intel Corporation

Inventor： Kristof DARMAWIKARTA ,  Benjamin DUONG ,  Srinivas V. PIETAMBARAM ,  Tarek A. IBRAHIM ,  Hari MAHALINGAM ,  Bai NIE

IPC: G02B6/122 ,  G02B6/13

Abstract: Embodiments disclosed herein include electronic packages with photonics integrated circuits (PICs). In an embodiment, an electronic package comprises a glass substrate with a first recess and a second recess. In an embodiment, a PIC is in the first recess. In an embodiment, an optics module is in the second recess, and an optical waveguide is embedded in the glass substrate between the first recess and the second recess. In an embodiment, the optical waveguide optically couples the PIC to the optics module.