公开(公告)号：US20210217873A1

公开(公告)日：2021-07-15

申请号：US16742295

申请日：2020-01-14

Applicant: International Business Machines Corporation

Inventor： Shahab Siddiqui ,  Koji Watanabe ,  Charlotte DeWan Adams ,  Kai Zhao ,  Daniel James Dechene ,  Rishikesh Krishnan

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8234

Abstract: A method of forming a semiconductor structure includes forming a first nanosheet stack and a second nanosheet stack on a semiconductor substrate. The first nanosheet stack includes a plurality of alternating first sacrificial layers and first channel layers. The first sacrificial layers each define a first sacrificial height. The second nanosheet stack includes a plurality of alternating second sacrificial layers and second channel layers. The second sacrificial layers each define a second sacrificial height greater than the first sacrificial height of the first sacrificial layers. The method further includes removing the first and second sacrificial layers respectively from the first and second nanosheet stacks. A metal gate is deposited over the first and second nanosheet stacks to form respective first and second nanosheet transistor structures.

公开(公告)号：US10243077B2

公开(公告)日：2019-03-26

申请号：US15820809

申请日：2017-11-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Eric C. Harley ,  Judson R. Holt ,  Yue Ke ,  Rishikesh Krishnan ,  Keith H. Tabakman ,  Henry K. Utomo

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165

Abstract: A method forming a semiconductor device that in one embodiment includes forming a gate structure on a channel region of fin structures, and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures.

公开(公告)号：US09917190B2

公开(公告)日：2018-03-13

申请号：US14884516

申请日：2015-10-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Eric C. Harley ,  Judson R. Holt ,  Yue Ke ,  Rishikesh Krishnan ,  Keith H. Tabakman ,  Henry K. Utomo

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

Abstract: A method forming a semiconductor device that in one embodiment includes forming a gate structure on a channel region of fin structures, and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures.

公开(公告)号：US09373524B2

公开(公告)日：2016-06-21

申请号：US14259657

申请日：2014-04-23

Applicant: International Business Machines Corporation

Inventor： Rishikesh Krishnan ,  Rajasekhar Venigalla

IPC: H01L21/302 ,  H01L21/321 ,  B24B37/04 ,  B24B37/20 ,  H01L21/3105

CPC classification number: H01L21/3212 ,  B24B37/04 ,  B24B37/20 ,  H01L21/31053

Abstract: A method of polishing a wafer at the die level with a targeted slurry delivery system. The wafer is placed on a wafer carrier exposing the top side of the wafer, the wafer contains a die. The polishing apparatus will polish a portion of the die using a pad that is smaller than the die and the pad is located above the die. A slurry is applied to a portion of the die being polished. Embodiments of the invention provide multiple pads working on the same die.

Abstract translation: 一种利用目标浆料输送系统在晶片级抛光晶片的方法。 将晶片放置在暴露晶片顶侧的晶片载体上，晶片包含晶片。 抛光装置将使用比模具更小的衬垫抛光模具的一部分，并且衬垫位于模具上方。 将浆料施加到待抛光的模具的一部分上。 本发明的实施例提供了在同一芯片上工作的多个焊盘。

公开(公告)号：US20160027640A1

公开(公告)日：2016-01-28

申请号：US14874386

申请日：2015-10-03

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Michael P. Chudzik ,  Min Dai ,  Martin M. Frank ,  David F. Hilscher ,  Rishikesh Krishnan ,  Barry P. Linder ,  Claude Ortolland ,  Joseph F. Shepard, JR.

IPC: H01L21/02 ,  H01L29/51 ,  H01L29/16 ,  H01L29/161 ,  H01L21/762

CPC classification number: H01L21/02301 ,  C23C16/0227 ,  C23C16/403 ,  C23C16/405 ,  C23C16/407 ,  C23C16/45525 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02247 ,  H01L21/02249 ,  H01L21/0228 ,  H01L21/02307 ,  H01L21/02312 ,  H01L21/28194 ,  H01L21/762 ,  H01L29/16 ,  H01L29/161 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: A surface of a semiconductor-containing dielectric material/oxynitride/nitride is treated with a basic solution in order to provide hydroxyl group termination of the surface. A dielectric metal oxide is subsequently deposited by atomic layer deposition. The hydroxyl group termination provides a uniform surface condition that facilitates nucleation and deposition of the dielectric metal oxide, and reduces interfacial defects between the oxide and the dielectric metal oxide. Further, treatment with the basic solution removes more oxide from a surface of a silicon germanium alloy with a greater atomic concentration of germanium, thereby reducing a differential in the total thickness of the combination of the oxide and the dielectric metal oxide across surfaces with different germanium concentrations.

Abstract translation: 用碱性溶液处理含半导体的电介质材料/氧氮化物/氮化物的表面，以提供表面的羟基终止。 随后通过原子层沉积沉积介电金属氧化物。 羟基终止提供了促进介电金属氧化物的成核和沉积的均匀的表面条件，并且减少了氧化物和介电金属氧化物之间的界面缺陷。 此外，用碱性溶液处理从锗锗合金的表面除去更多的锗原子浓度的锗，从而减少氧化物和电介质金属氧化物的组合的总厚度与不同锗的表面的差异 浓度

公开(公告)号：US20150371870A1

公开(公告)日：2015-12-24

申请号：US14839358

申请日：2015-08-28

Applicant: International Business Machines Corporation

Inventor： Rishikesh Krishnan ,  Rajasekhar Venigalla

IPC: H01L21/321

CPC classification number: H01L21/3212 ,  B24B37/04 ,  B24B37/20 ,  H01L21/31053

Abstract: A method of polishing a wafer at the die level with a targeted slurry delivery system. The wafer is placed on a wafer carrier exposing the top side of the wafer, the wafer contains a die. The polishing apparatus will polish a portion of the die using a pad that is smaller than the die and the pad is located above the die. A slurry is applied to a portion of the die being polished. Embodiments of the invention provide multiple pads working on the same die.

Abstract translation: 一种利用目标浆料输送系统在晶片级抛光晶片的方法。 将晶片放置在暴露晶片顶侧的晶片载体上，晶片包含晶片。 抛光装置将使用比模具更小的衬垫抛光模具的一部分，并且衬垫位于模具上方。 将浆料施加到待抛光的模具的一部分上。 本发明的实施例提供了在同一芯片上工作的多个焊盘。

公开(公告)号：US20150364362A1

公开(公告)日：2015-12-17

申请号：US14306598

申请日：2014-06-17

Applicant: International Business Machines Corporation

Inventor： Edward Engbrecht ,  Donghun Kang ,  Rishikesh Krishnan ,  Oh-jung Kwon ,  Karen A. Nummy

IPC: H01L21/762 ,  H01L21/66 ,  H01L29/06 ,  H01L21/308 ,  H01L21/321

CPC classification number: H01L21/76227 ,  H01L21/302 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3212 ,  H01L22/12 ,  H01L29/0603 ,  H01L29/945

Abstract: Embodiments of the present invention provide structures and methods for controlling stress in semiconductor wafers during fabrication. Features such as deep trenches (DTs) used in circuit elements such as trench capacitors impart stress on a wafer that is proportional to the surface area of the DTs. In embodiments, a corresponding pattern of dummy (non-functional) DTs is formed on the back side of the wafer to counteract the electrically functional DTs formed on the front side of a wafer. In some embodiments, the corresponding pattern on the back side is a mirror pattern that matches the functional (front side) pattern in size, placement, and number. By creating the minor pattern on both sides of the wafer, the stresses on the front and back of the wafer are in balance. This helps reduce topography issues such as warping that can cause problems during wafer fabrication.

Abstract translation: 本发明的实施例提供了在制造期间控制半导体晶片中的应力的结构和方法。 诸如沟槽电容器的电路元件中使用的诸如深沟槽（DT）的特征赋予与DT的表面积成比例的晶片上的应力。 在实施例中，虚拟（非功能）DT的相应图案形成在晶片的背面，以抵消形成在晶片正面上的电功能DT。 在一些实施例中，背面上的对应图案是与尺寸，布局和数量上的功能（前侧）图案相匹配的镜面图案。 通过在晶片的两侧形成次要图案，晶片正面和背面的应力平衡。 这有助于减少在晶圆制造过程中可能导致问题的翘曲等形貌问题。

公开(公告)号：US20150357402A1

公开(公告)日：2015-12-10

申请号：US14831487

申请日：2015-08-20

Applicant: International Business Machines Corporation

Inventor： Nicolas L. Breil ,  Ricardo A. Donaton ,  Dong Hun Kang ,  Herbert L. Ho ,  Rishikesh Krishnan

IPC: H01L49/02 ,  H01L21/283

CPC classification number: H01L28/91 ,  H01L21/283 ,  H01L27/1082 ,  H01L27/10832 ,  H01L27/10858 ,  H01L27/10867 ,  H01L27/1087 ,  H01L28/90

Abstract: Method of forming a deep trench capacitor are provided. The method may include forming a deep trench in a substrate; forming a metal-insulator-metal (MIM) stack within a portion of the deep trench, the MIM stack forming including forming an outer electrode by co-depositing a refractory metal and silicon into the deep trench; and filling a remaining portion of the deep trench with a semiconductor.

Abstract translation: 提供形成深沟槽电容器的方法。 该方法可以包括在衬底中形成深沟槽; 在所述深沟槽的一部分内形成金属 - 绝缘体 - 金属（MIM）堆叠，所述MIM堆叠形成包括通过将难熔金属和硅共沉积到所述深沟槽中而形成外电极; 以及用半导体填充深沟槽的剩余部分。

公开(公告)号：US20150311088A1

公开(公告)日：2015-10-29

申请号：US14259657

申请日：2014-04-23

Applicant: International Business Machines Corporation

Inventor： Rishikesh Krishnan ,  Rajasekhar Venigalla

IPC: H01L21/306 ,  B24B37/20 ,  H01L21/67 ,  B24B37/04

CPC classification number: H01L21/3212 ,  B24B37/04 ,  B24B37/20 ,  H01L21/31053

Abstract: A method of polishing a wafer at the die level with a targeted slurry delivery system. The wafer is placed on a wafer carrier exposing the top side of the wafer, the wafer contains a die. The polishing apparatus will polish a portion of the die using a pad that is smaller than the die and the pad is located above the die. A slurry is applied to a portion of the die being polished. Embodiments of the invention provide multiple pads working on the same die.

公开(公告)号：US20140183051A1

公开(公告)日：2014-07-03

申请号：US13732642

申请日：2013-01-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael P. Chudzik ,  Min Dai ,  Rishikesh Krishnan ,  Joseph F. Shepard, JR.

IPC: C25D3/54

CPC classification number: C25D3/54 ,  C25D5/00 ,  C25D5/003 ,  C25D17/001 ,  C25D17/002

Abstract: A system and method generate atomic hydrogen (H) for deposition of a pure metal in a three-dimensional (3D) structure. The method includes forming a monolayer of a compound that includes the pure metal. The method also includes depositing the monolayer on the 3D structure and immersing the 3D structure with the monolayer in an electrochemical cell chamber including an electrolyte. Applying a negative bias voltage to the 3D structure with the monolayer and a positive bias voltage to a counter electrode generates atomic hydrogen from the electrolyte and deposits the pure metal from the monolayer in the 3D structure.

Abstract translation: 一种系统和方法产生用于在三维（3D）结构中沉积纯金属的原子氢（H）。 该方法包括形成包含纯金属的化合物的单层。 该方法还包括在3D结构上沉积单层并将具有单层的3D结构浸入包括电解质的电化学电池室中。 使用单层将三角形结构施加负偏置电压并对正电极施加正偏置电压，从电解液中产生原子氢，并在3D结构中从单层沉积纯金属。