Dice before grind with backside metal
    11.
    发明授权
    Dice before grind with backside metal 有权
    研磨前的骰子与背面金属

    公开(公告)号:US09165831B2

    公开(公告)日:2015-10-20

    申请号:US13928676

    申请日:2013-06-27

    CPC classification number: H01L21/78 H01L21/283

    Abstract: A method including forming a plurality of dicing channels in a front side of a wafer; the plurality of dicing channels including a depth at least greater than a desired final thickness of the wafer, filling the plurality of dicing channels with a fill material and removing a portion of the wafer from a back side of the wafer until the desired final thickness is achieved, where a portion of the fill material within the plurality of dicing channel is exposed. The method further including depositing a metal layer on the back side of the wafer; removing the fill material from within the plurality of dicing channels to expose the metal layer at a bottom of the plurality of dicing channels, and removing a portion of the metal layer located at the bottom of the plurality of dicing channels.

    Abstract translation: 一种包括在晶片的前侧形成多个切割通道的方法; 多个切割通道包括至少大于晶片的期望最终厚度的深度,用填充材料填充多个切割通道,并从晶片的背面去除晶片的一部分,直到期望的最终厚度为 其中多个切割通道内的填充材料的一部分被暴露。 该方法还包括在晶片的背面沉积金属层; 从所述多个切割通道内移除所述填充材料以暴露所述多个切割通道的底部处的所述金属层,以及去除位于所述多个切割通道的底部的所述金属层的一部分。

    INTEGRATED CIRCUIT STRUCTURE WITH THROUGH-SEMICONDUCTOR VIA
    13.
    发明申请
    INTEGRATED CIRCUIT STRUCTURE WITH THROUGH-SEMICONDUCTOR VIA 有权
    通过半导体的集成电路结构

    公开(公告)号:US20150115460A1

    公开(公告)日:2015-04-30

    申请号:US14065454

    申请日:2013-10-29

    Abstract: The present disclosure generally provides for integrated circuit (IC) structures with through-semiconductor vias (TSV). In an embodiment, an IC structure may include a through-semiconductor via (TSV) embedded in a substrate, the TSV having a cap; a dielectric layer adjacent to the substrate; a metal layer adjacent to the dielectric layer; a plurality of vias each embedded within the dielectric layer and coupling the metal layer to the cap of the TSV at respective contact points, wherein the plurality of vias is configured to create a substantially uniform current density throughout the TSV.

    Abstract translation: 本公开通常提供具有贯穿半导体通孔(TSV)的集成电路(IC)结构。 在一个实施例中,IC结构可以包括嵌入在衬底中的贯穿半导体通孔(TSV),TSV具有帽; 与基板相邻的电介质层; 与介电层相邻的金属层; 多个通孔,每个通孔嵌入在电介质层内,并将金属层耦合到各个接触点处的TSV的盖,其中多个通孔被配置成在整个TSV中产生基本均匀的电流密度。

    CONTROLLED METAL EXTRUSION OPENING IN SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING
    20.
    发明申请
    CONTROLLED METAL EXTRUSION OPENING IN SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING 有权
    半导体结构中的控制金属挤压开口和形成方法

    公开(公告)号:US20150255395A1

    公开(公告)日:2015-09-10

    申请号:US14718466

    申请日:2015-05-21

    Abstract: Aspects of the present invention relate to a controlled metal extrusion opening in a semiconductor structure. Various embodiments include a semiconductor structure. The structure includes an aluminum layer. The aluminum layer includes an aluminum island within the aluminum layer, and a lateral extrusion receiving opening extending through the aluminum layer adjacent the aluminum island. The opening includes a lateral extrusion of the aluminum layer of the semiconductor structure. Additional embodiments include a method of forming a semiconductor structure. The method can include forming an aluminum layer over a titanium layer. The aluminum layer includes an aluminum island within the aluminum layer. The method can also include forming an opening extending through the aluminum layer adjacent the aluminum island within the aluminum layer. The opening includes a lateral extrusion of the aluminum layer of the semiconductor layer.

    Abstract translation: 本发明的方面涉及半导体结构中的受控金属挤压开口。 各种实施例包括半导体结构。 该结构包括铝层。 铝层包括在铝层内的铝岛,以及横向挤压接收开口,其延伸穿过靠近铝岛的铝层。 该开口包括半导体结构的铝层的横向挤压。 另外的实施例包括形成半导体结构的方法。 该方法可以包括在钛层上形成铝层。 铝层包括铝层内的铝岛。 该方法还可以包括在铝层内形成延伸穿过邻近铝岛的铝层的开口。 该开口包括半导体层的铝层的侧向挤压。

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