公开(公告)号：US20060051961A1

公开(公告)日：2006-03-09

申请号：US10935497

申请日：2004-09-07

申请人： Cyril Cabral ,  Michael Cobb ,  Balasubramanian Pranatharthi Haran ,  Randolph Knarr ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Andrew Mansson ,  Horatio Wildman

发明人： Cyril Cabral ,  Michael Cobb ,  Balasubramanian Pranatharthi Haran ,  Randolph Knarr ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Andrew Mansson ,  Horatio Wildman

IPC分类号： H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/28052 ,  H01L29/665

摘要： The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a conductive Ni alloy with Pt and optionally at least one of the following metals Pd, Rh, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W or Re over an entire semiconductor structure which includes at least one gate stack region. An oxygen diffusion barrier comprising, for example, Ti, TiN or W is deposited over the structure to prevent oxidation of the metals. An annealing step is then employed to cause formation of a NiSi, PtSi contact in regions in which the metals are in contact with silicon. The metal that is in direct contact with insulating material such as SiO2 and Si3N4 is not converted into a metal alloy silicide contact during the annealing step. A selective etching step is then performed to remove unreacted metal from the sidewalls of the spacers and trench isolation regions.

摘要翻译： 本发明提供一种形成自对准Ni合金硅化物接触的方法。 本发明的方法首先首先用Pt和任选的以下金属Pd，Rh，Ti，V，Cr，Zr，Nb，Mo，Hf，Ta，W或Re中的至少一种沉积导电Ni合金， 整个半导体结构，其包括至少一个栅极堆叠区域。 包含例如Ti，TiN或W的氧扩散阻挡层沉积在结构上以防止金属的氧化。 然后使用退火步骤在金属与硅接触的区域中形成NiSi，PtSi接触。 与诸如SiO 2和Si 3 N 4 N之类的绝缘材料直接接触的金属在金属合金硅化物接触期间不会转化为金属合金硅化物接触 退火步骤。 然后执行选择性蚀刻步骤以从间隔物和沟槽隔离区域的侧壁去除未反应的金属。

公开(公告)号：US20050051854A1

公开(公告)日：2005-03-10

申请号：US10605106

申请日：2003-09-09

申请人： Cyril Cabral ,  Paul Jamison ,  Victor Ku ,  Ying Li ,  Vijay Narayanan ,  An Steegen ,  Yun-Yu Wang ,  Kwong Wong

发明人： Cyril Cabral ,  Paul Jamison ,  Victor Ku ,  Ying Li ,  Vijay Narayanan ,  An Steegen ,  Yun-Yu Wang ,  Kwong Wong

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L21/20 ,  H01L21/8234 ,  H01L29/76 ,  H01L31/062

CPC分类号： H01L29/66545 ,  H01L21/28079 ,  H01L29/4958

摘要： A structure and method for a metal replacement gate of a high performance device is provided. A sacrificial gate structure is first formed on an etch stop layer provided on a semiconductor substrate. A pair of spacers is provided on sidewalls of the sacrificial gate structure. The sacrificial gate structure is then removed, forming an opening. Subsequently, a metal gate including an first layer of metal such as tungsten, a diffusion barrier such as titanium nitride, and a second layer of metal such as tungsten is formed in the opening between the spacers.

摘要翻译： 提供了一种用于高性能器件的金属替换栅极的结构和方法。 首先在设置在半导体衬底上的蚀刻停止层上形成牺牲栅极结构。 在牺牲栅极结构的侧壁上设置一对间隔物。 然后去除牺牲栅极结构，形成开口。 随后，在间隔件之间的开口中形成包括诸如钨的第一金属层的金属栅，诸如氮化钛的扩散阻挡层和诸如钨的第二金属层。

公开(公告)号：US20080217700A1

公开(公告)日：2008-09-11

申请号：US11684619

申请日：2007-03-11

申请人： Bruce B. Doris ,  Cyril Cabral ,  Elizabeth A. Duch ,  Stephen M. Rossnagel ,  Michelle L. Steen

发明人： Bruce B. Doris ,  Cyril Cabral ,  Elizabeth A. Duch ,  Stephen M. Rossnagel ,  Michelle L. Steen

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823842 ,  H01L29/4958 ,  H01L29/7845

摘要： NFET and PFET devices with separately stressed channel regions, and methods of their fabrication is disclosed. A FET is disclosed which includes a gate, which gate includes a metal in a first state of stress. The FET also includes a channel region hosted in a single crystal Si based material, which channel region is overlaid by the gate and is in a second state of stress. The second state of stress of the channel region is of an opposite sign than the first state of stress of the metal included in the gate. The NFET channel is usually in a tensile state of stress, while the PFET channel is usually in a compressive state of stress. The methods of fabrication include the deposition of metal layers by physical vapor deposition (PVD), in such manner that the layers are in stressed states.

摘要翻译： 具有单独应力通道区域的NFET和PFET器件及其制造方法。 公开了一种FET，其包括栅极，该栅极包括处于第一应力状态的金属。 FET还包括托管在单晶Si基材料中的沟道区域，该沟道区域被栅极覆盖并处于第二应力状态。 沟道区域的第二应力状态与包括在栅极中的金属的第一应力状态相反。 NFET通道通常处于应力的拉伸状态，而PFET通道通常处于应力的压缩状态。 制造方法包括通过物理气相沉积（PVD）沉积金属层，使得层处于应力状态。

公开(公告)号：US20080164584A1

公开(公告)日：2008-07-10

申请号：US12051040

申请日：2008-03-19

申请人： Cyril Cabral ,  Michael S. Gordon ,  Kenneth P. Rodbell

发明人： Cyril Cabral ,  Michael S. Gordon ,  Kenneth P. Rodbell

IPC分类号： H01L23/556 ,  G01R31/26 ,  G06F17/50

CPC分类号： H01L23/556 ,  H01L21/76801 ,  H01L21/76834 ,  H01L21/76838 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/12 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05006 ,  H01L2224/05554 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01055 ,  H01L2924/01057 ,  H01L2924/01063 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/01092 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15312 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/05552

摘要： A structure and a method for reduction of soft error rates in integrated circuits. The structure including: a semiconductor substrate; and a stack of one or more wiring levels stacked from a lowermost wiring level to an uppermost wiring level, the lowermost wiring level nearer the semiconductor substrate than the uppermost wiring level; and an alpha particle blocking layer on a top surface of the uppermost wiring level of the one or more wiring levels, the blocking layer comprising metal wires and a dielectric material, the blocking layer having a combination of a thickness of the blocking layer and a volume percent of metal wires in the blocking layer sufficient to stop a predetermined percentage of alpha particles of a selected energy or less striking the blocking layer from penetrating into the stack of one or more wiring levels or the substrate.

摘要翻译： 降低集成电路中软错误率的结构和方法。 该结构包括：半导体衬底; 以及从最下布线电平堆叠到最上布线电平的一个或多个布线电平的堆叠，比最上布线电平更靠近半导体基板的最下布线电平; 以及在所述一个或多个布线层的最上布线层的顶表面上的α粒子阻挡层，所述阻挡层包括金属线和介电材料，所述阻挡层具有阻挡层的厚度和体积 阻挡层中的金属线的百分比足以阻止预定百分比的选定能量的α粒子或更少的击穿阻挡层的金属线穿透到一个或多个布线层或衬底的堆叠中。

公开(公告)号：US20080026551A1

公开(公告)日：2008-01-31

申请号：US11830277

申请日：2007-07-30

申请人： Cyril Cabral ,  Chester Dziobkowski ,  Sunfei Fang ,  Evgeni Gousev ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Ghavam Shahidi ,  Michelle Steen ,  Clement Wann

发明人： Cyril Cabral ,  Chester Dziobkowski ,  Sunfei Fang ,  Evgeni Gousev ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Ghavam Shahidi ,  Michelle Steen ,  Clement Wann

IPC分类号： H01L21/3205

CPC分类号： H01L29/66507 ,  H01L21/28097 ,  H01L21/823443 ,  H01L29/66545

摘要： An advanced gate structure that includes a filly silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. A method of forming the advanced gate structure is also provided in which the silicided source and drain regions are formed prior to formation of the silicided metal gate region.

摘要翻译： 提供了一种先进的栅极结构，其包括硅化金属栅极和硅化源极和漏极区域，其中完全硅化金属栅极的厚度大于硅化物源极/漏极区域的厚度。 还提供了形成高级栅极结构的方法，其中在形成硅化金属栅极区之前形成硅化源极和漏极区。

公开(公告)号：US20070111421A1

公开(公告)日：2007-05-17

申请号：US11618751

申请日：2006-12-30

申请人： Cyril Cabral ,  Bruce Doris ,  Thomas Kanarsky ,  Xiao Liu ,  Huilong Zhu

发明人： Cyril Cabral ,  Bruce Doris ,  Thomas Kanarsky ,  Xiao Liu ,  Huilong Zhu

IPC分类号： H01L21/8238

CPC分类号： H01L29/7845 ,  H01L21/3215 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665

摘要： A semiconductor structure and method that is capable of generating a local mechanical gate stress for channel mobility modification are provided. The semiconductor structure includes at least one NFET and at least one PFET on a surface of a semiconductor substrate. The at least one NFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer, a Si-containing second gate electrode layer and a compressive metal, and the at least one PFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer and a tensile metal or a silicide.

摘要翻译： 提供了能够产生用于信道迁移率修改的局部机械栅极应力的半导体结构和方法。 半导体结构在半导体衬底的表面上包括至少一个NFET和至少一个PFET。 所述至少一个NFET具有包括栅极电介质，第一栅极电极层，阻挡层，含Si的第二栅极电极层和压缩金属的栅极堆叠结构，并且所述至少一个PFET具有包括 栅极电介质，第一栅电极层，阻挡层和拉伸金属或硅化物。

公开(公告)号：US20060189061A1

公开(公告)日：2006-08-24

申请号：US11407313

申请日：2006-04-19

申请人： Ricky Amos ,  Diane Boyd ,  Cyril Cabral ,  Richard Kaplan ,  Jakub Kedzierski ,  Victor Ku ,  Woo-Hyeong Lee ,  Ying Li ,  Anda Mocuta ,  Vijay Narayanan ,  An Steegen ,  Maheswaren Surendra

发明人： Ricky Amos ,  Diane Boyd ,  Cyril Cabral ,  Richard Kaplan ,  Jakub Kedzierski ,  Victor Ku ,  Woo-Hyeong Lee ,  Ying Li ,  Anda Mocuta ,  Vijay Narayanan ,  An Steegen ,  Maheswaren Surendra

IPC分类号： H01L21/8238

CPC分类号： H01L21/76897 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823835 ,  H01L29/66545 ,  H01L29/6656

摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.

摘要翻译： 本发明提供了一种互补金属氧化物半导体集成工艺，其中在栅极电介质顶部制造多个硅化金属栅极。 使用本发明的集成方案形成的每个硅化金属栅极与硅化物金属栅极的尺寸无关，具有相同的硅化物金属相和基本上相同的高度。 本发明还提供了形成具有硅化物触点的CMOS结构的各种方法，其中多晶硅栅极高度在半导体结构的整个表面上基本相同。

公开(公告)号：US20060138603A1

公开(公告)日：2006-06-29

申请号：US11281032

申请日：2005-11-17

申请人： Cyril Cabral ,  Alessandro Callegari ,  Michael Gribelyuk ,  Paul Jamison ,  Dianne Lacey ,  Fenton McFeely ,  Vijay Narayanan ,  Deborah Neumayer ,  Pushkar Ranade ,  Sufi Zafar

发明人： Cyril Cabral ,  Alessandro Callegari ,  Michael Gribelyuk ,  Paul Jamison ,  Dianne Lacey ,  Fenton McFeely ,  Vijay Narayanan ,  Deborah Neumayer ,  Pushkar Ranade ,  Sufi Zafar

IPC分类号： H01L23/58

CPC分类号： H01L21/02181 ,  C23C16/405 ,  C23C16/56 ,  H01L21/02189 ,  H01L21/02205 ,  H01L21/02271 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/31604 ,  H01L21/823857 ,  H01L27/0805 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating hafnium oxide and/or zirconium oxide films is provided. The methods include providing a mixture of Hf and/or Zr alkoxide dissolved, emulsified or suspended in a liquid; vaporizing at least the alkoxide and depositing the vaporized component at a temperature of greater than 400° C. The resultant film is dense, microcrystalline and is capable of self-passivation when treated in a hydrogen plasma or forming gas anneal.

公开(公告)号：US20060121662A1

公开(公告)日：2006-06-08

申请号：US10904884

申请日：2004-12-02

申请人： Sunfei Fang ,  Cyril Cabral ,  Chester Dziobkowski ,  John Ellis-Monaghan ,  Christian Lavoie ,  Zhijiong Luo ,  James Nakos ,  An Steegen ,  Clement Wann

发明人： Sunfei Fang ,  Cyril Cabral ,  Chester Dziobkowski ,  John Ellis-Monaghan ,  Christian Lavoie ,  Zhijiong Luo ,  James Nakos ,  An Steegen ,  Clement Wann

IPC分类号： H01L21/8238 ,  H01L21/3205 ,  H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/823814 ,  H01L21/823835

摘要： A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.

公开(公告)号：US20050186747A1

公开(公告)日：2005-08-25

申请号：US10786901

申请日：2004-02-25

申请人： Ricky Amos ,  Diane Boyd ,  Cyril Cabral ,  Richard Kaplan ,  Jakub Kedzierski ,  Victor Ku ,  Woo-Hyeong Lee ,  Ying Li ,  Anda Mocuta ,  Vijay Narayanan ,  An Steegen ,  Maheswaran Surendra

发明人： Ricky Amos ,  Diane Boyd ,  Cyril Cabral ,  Richard Kaplan ,  Jakub Kedzierski ,  Victor Ku ,  Woo-Hyeong Lee ,  Ying Li ,  Anda Mocuta ,  Vijay Narayanan ,  An Steegen ,  Maheswaran Surendra

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/339 ,  H01L21/60 ,  H01L21/8238

CPC分类号： H01L21/76897 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823835 ,  H01L29/66545 ,  H01L29/6656

摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.

摘要翻译： 本发明提供了一种互补金属氧化物半导体集成工艺，其中在栅极电介质顶部制造多个硅化金属栅极。 使用本发明的集成方案形成的每个硅化金属栅极与硅化物金属栅极的尺寸无关，具有相同的硅化物金属相和基本上相同的高度。 本发明还提供了形成具有硅化物触点的CMOS结构的各种方法，其中多晶硅栅极高度在半导体结构的整个表面上基本相同。