公开(公告)号：US20060220083A1

公开(公告)日：2006-10-05

申请号：US11306387

申请日：2005-12-27

Applicant: Kazuhide Abe

Inventor： Kazuhide Abe

IPC: H01L29/94

CPC classification number: H01L27/11502 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/32136 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76858 ,  H01L21/76864 ,  H01L21/7687 ,  H01L21/76877 ,  H01L27/11507 ,  H01L28/65 ,  H01L28/75

Abstract: A semiconductor device includes a semiconductor substrate, a first electrode that is formed over said semiconductor substrate, a capacitive insulating film that is formed on the first electrode and is made of a metal oxide ferroelectric, a second electrode that is formed on the capacitive insulating film, an insulating film that has a first opening exposing a portion of an upper side of the second electrode and is formed so that it covers the first electrode, the capacitive insulating film, and the second electrode, a first barrier film having an amorphous structure which is formed inside the first opening and on the insulating film, and a wiring film that is formed over the first barrier film.

Abstract translation: 半导体器件包括半导体衬底，形成在所述半导体衬底上的第一电极，形成在第一电极上并由金属氧化物铁电体制成的电容绝缘膜，形成在电容绝缘膜上的第二电极 绝缘膜，其具有暴露第二电极的上侧的一部分并且形成为使得其覆盖第一电极，电容绝缘膜和第二电极的第一开口，具有非晶结构的第一阻挡膜， 形成在第一开口内部和绝缘膜上，以及形成在第一阻挡膜上的布线膜。

公开(公告)号：US20060055287A1

公开(公告)日：2006-03-16

申请号：US11196596

申请日：2005-08-04

Applicant: Takashi Kawakubo ,  Toshihiko Nagano ,  Kazuhide Abe ,  Michihiko Nishigaki

Inventor： Takashi Kawakubo ,  Toshihiko Nagano ,  Kazuhide Abe ,  Michihiko Nishigaki

IPC: H01L41/04

CPC classification number: H01H57/00 ,  H01G5/18 ,  H01G5/38 ,  H01H2057/006 ,  H01L41/094 ,  H01L41/0946 ,  H01L41/0953 ,  Y10S977/837

Abstract: A piezoelectric actuator includes a first beam including a first bottom electrode, a first piezoelectric film on the first bottom electrode, and a first top electrode on the first piezoelectric film, a fixed end assigned at an end of the first beam and fixed on a substrate, a connecting end assigned at another end of the first beam and suspended over a free space; and a second beam including a second piezoelectric film connected to the first piezoelectric film at the connecting end, a second bottom electrode under the second piezoelectric film, and a second top electrode on the second piezoelectric film, a working end assigned at an end of the second beam opposite to another end to which the connecting end is assigned and suspended over the free space; wherein a distance between centers of the fixed end and the working end is shorter than a distance from the working end to the connecting end.

Abstract translation: 压电致动器包括第一梁，该第一梁包括第一底电极，第一底电极上的第一压电膜和第一压电膜上的第一顶电极，分配在第一梁的端部并固定在基板上的固定端 ，分配在第一梁的另一端并悬挂在自由空间上的连接端; 以及第二光束，包括在连接端连接到第一压电膜的第二压电膜，第二压电膜下的第二底电极和第二压电膜上的第二顶电极，分配在第二压电膜的端部的工作端 第二梁相对于连接端被分配并悬挂在自由空间上的另一端; 其中固定端和工作端的中心之间的距离短于从工作端到连接端的距离。

公开(公告)号：US20050151224A1

公开(公告)日：2005-07-14

申请号：US10910318

申请日：2004-08-04

Applicant: Kazuhide Abe

Inventor： Kazuhide Abe

IPC: H01L21/288 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/532 ,  H01L29/00

CPC classification number: H01L23/5226 ,  H01L21/2885 ,  H01L21/31116 ,  H01L21/3212 ,  H01L21/32135 ,  H01L21/32136 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76877 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device has a semiconductor substrate, a first insulating film formed on a surface of the semiconductor substrate, a first recess formed in the first insulating film, a first barrier film formed on an inner surface of the first insulating film except a top peripheral region of the first trench, a first conductive film formed in the first trench, and a covering film formed on an upper surface and a top peripheral region of the first conductive film and an upper surface of the first barrier film. The first conductive film includes copper.

Abstract translation: 半导体器件具有半导体衬底，形成在半导体衬底的表面上的第一绝缘膜，形成在第一绝缘膜中的第一凹槽，形成在除了顶部周边区域之外的第一绝缘膜的内表面上的第一阻挡膜 形成在第一沟槽中的第一导电膜和形成在第一导电膜的上表面和顶周边区域上的覆盖膜和第一阻挡膜的上表面。 第一导电膜包括铜。

公开(公告)号：US20050087872A1

公开(公告)日：2005-04-28

申请号：US10766739

申请日：2004-01-29

Applicant: Kazuhide Abe

Inventor： Kazuhide Abe

IPC: H01L21/288 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L23/48

CPC classification number: H01L21/76843 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The wiring structure of a semiconductor device of the invention enhances the dielectric strength of the wirings and reduces the capacitance across the wirings, by preventing a diffusion of the wiring material. The wiring structure includes a first insulating film, plural wiring films, plural barrier films, and plural cap films. The first insulating film has plural grooves formed thereon, and has an interface in the horizontal direction between the adjoining grooves. The wiring films are formed to protrude from the interface each by the grooves of the first insulating film. The barrier films are formed on the bottoms of the wiring films, and also on side faces of the wiring films to a height exceeding the interface. The cap films are formed at least on the upper faces of the wiring films, and are separated each by the grooves.

Abstract translation: 本发明的半导体器件的布线结构通过防止布线材料的扩散，增强布线的介电强度并降低布线两端的电容。 布线结构包括第一绝缘膜，多个布线膜，多个阻挡膜和多个盖膜。 第一绝缘膜具有形成在其上的多个槽，并且在相邻的槽之间具有在水平方向上的界面。 布线膜形成为从第一绝缘膜的沟槽各自的界面突出。 阻挡膜形成在布线膜的底部以及布线膜的侧面上，达到超过界面的高度。 盖膜至少形成在布线膜的上表面上，并由沟槽分开。

公开(公告)号：US06870446B2

公开(公告)日：2005-03-22

申请号：US10252105

申请日：2002-09-23

Applicant: Ryoichi Ohara ,  Kazuhide Abe ,  Takashi Kawakubo ,  Hiroshi Yoshida ,  Hiroshi Tsurumi ,  Ryuichi Fujimoto

Inventor： Ryoichi Ohara ,  Kazuhide Abe ,  Takashi Kawakubo ,  Hiroshi Yoshida ,  Hiroshi Tsurumi ,  Ryuichi Fujimoto

IPC: H03H9/00 ,  H03H9/54 ,  H03H9/58 ,  H03H9/60

CPC classification number: H03H9/605 ,  H03H9/0095 ,  H03H9/542 ,  H03H9/581 ,  H03H2009/02196

Abstract: A high frequency filter comprises thin film piezoelectric resonators connected in series between the input/output nodes, thin film piezoelectric resonators connected in parallel between the input/output nodes and a variable voltage circuit adapted to change the voltage applied to at least either the thin film piezoelectric resonators connected in series or the thin film piezoelectric resonators connected in parallel. The resonance characteristic of at least either the thin film piezoelectric resonators connected in series or the thin film piezoelectric resonator connected in parallel is shifted by changing the voltage applied by the variable voltage circuit to change the pass characteristic of the filter.

Abstract translation: 高频滤波器包括串联连接在输入/输出节点之间的薄膜压电谐振器，并联连接在输入/输出节点之间的薄膜压电谐振器和可变电压电路，可变电压电路适于改变施加到至少薄膜的电压 串联连接的压电谐振器或并联连接的薄膜压电谐振器。 串联连接的薄膜压电谐振器或并联连接的薄膜压电谐振器中的至少一个的谐振特性通过改变由可变电压电路施加的电压来改变滤波器的通过特性而被移位。

公开(公告)号：US06809604B2

公开(公告)日：2004-10-26

申请号：US10397876

申请日：2003-03-27

Applicant: Takashi Kawakubo ,  Ryoichi Ohara ,  Kazuhide Abe ,  Hiroshi Tsurumi ,  Hiroshi Yoshida ,  Ryuichi Fujimoto

Inventor： Takashi Kawakubo ,  Ryoichi Ohara ,  Kazuhide Abe ,  Hiroshi Tsurumi ,  Hiroshi Yoshida ,  Ryuichi Fujimoto

IPC: H03B532

CPC classification number: H03H9/173 ,  H03H9/0095 ,  H03H9/545 ,  H03H9/562 ,  H03H9/564 ,  H03H9/566 ,  H03H9/581 ,  H03H9/585 ,  H03H9/60 ,  H03H2009/02196

Abstract: To provide a miniaturized voltage controlled oscillator which can oscillate simultaneously a plurality of frequencies and has high stability of frequency, an excellent low phase noise, small variation per hour, and a wide frequency variable range. A thin film bulk acoustic wave resonator using single crystal ferroelectric material equal to or smaller than 10 &mgr;m in thickness whose direction of polarization is aligned to the direction of thickness is utilized as the piezoelectric member. The voltage controlled oscillator having large changing rate of the oscillation frequency of 0.01%/V or more and an extremely small phase noise is provided by changing the voltage applied to the electrodes.

Abstract translation: 为了提供能够同时振荡多个频率并且具有高的频率稳定性，优异的低相位噪声，小时变化小和宽频率可变范围的微型压控振荡器.1。一种使用单晶的薄膜体声波谐振器 作为压电部件，利用等于或小于10μm厚的偏振方向与厚度方向对准的铁电材料。 通过改变施加到电极上的电压，提供振荡频率变化率大于0.01％/ V以上且极小相位噪声的压控振荡器。

公开(公告)号：US5889696A

公开(公告)日：1999-03-30

申请号：US45958

申请日：1998-03-23

Applicant: Takashi Kawakubo ,  Noburu Fukushima ,  Kazuhide Abe

Inventor： Takashi Kawakubo ,  Noburu Fukushima ,  Kazuhide Abe

IPC: H01L27/10 ,  G11C11/22 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108

CPC classification number: G11C11/22

Abstract: A semiconductor memory device is constituted by arranging a plurality of memory cells in a matrix format, each of which includes a thin-film capacitor having a ferroelectric film and a pair of electrodes facing each other via the ferroelectric film, and a transfer gate transistor connected to the thin film capacitor. A voltage corresponding to the width of a hysteresis curve obtained when the thin-film capacitor is saturated and polarized falls within the range of 5% or higher to 20% or lower of the voltage difference between the positive and negative directions in a writing operation. A remanent polarization amount obtained when the thin-film capacitor is saturated and polarized falls within the range of 5% or higher to 30% or lower of the total polarization amount obtained upon application of a voltage in the writing operation.

Abstract translation: 半导体存储器件通过以矩阵形式布置多个存储单元而构成，每个存储单元包括具有铁电膜的薄膜电容器和经由铁电体膜相互面对的一对电极，并且连接有传输栅极晶体管 到薄膜电容器。 当薄膜电容器饱和和极化时获得的滞后曲线的宽度对应的电压落在写入操作中正负方向之间的电压差的5％以上至20％以下的范围内。 当薄膜电容器饱和和极化时获得的剩余极化量落在在写入操作中施加电压时获得的总极化量的5％以上至30％以下的范围内。

公开(公告)号：US09041182B2

公开(公告)日：2015-05-26

申请号：US13688823

申请日：2012-11-29

Applicant: Toshihiko Nagano ,  Kazuhide Abe ,  Hiroshi Yamada ,  Kazuhiko Itaya ,  Taihei Nakada

Inventor： Toshihiko Nagano ,  Kazuhide Abe ,  Hiroshi Yamada ,  Kazuhiko Itaya ,  Taihei Nakada

IPC: H01L23/48 ,  H01L21/78 ,  H01L23/055 ,  H01L23/10 ,  H01L23/00 ,  H01L23/66

CPC classification number: H01L23/48 ,  H01L21/78 ,  H01L23/055 ,  H01L23/10 ,  H01L23/66 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/13007 ,  H01L2224/13111 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/14181 ,  H01L2224/16235 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81205 ,  H01L2224/814 ,  H01L2224/81411 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/81895 ,  H01L2224/81986 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1461 ,  H01L2924/1515 ,  H01L2924/15788 ,  H01L2924/16153 ,  H01L2224/81 ,  H01L2924/01079 ,  H01L2924/01014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor package according to embodiments includes: a semiconductor chip including a front electrode on a front surface thereof and a back electrode on a back surface thereof; a front-side cap portion including an air gap in a portion between the semiconductor chip and the front-side cap portion and a front-side penetrating electrode, and is positioned to face the front surface of the semiconductor chip; a back-side cap portion bonded with a first cap portion to hermetically seal the semiconductor chip, includes an air gap at least in a portion between the semiconductor chip and the back-side cap portion and a back-side penetrating electrode, and is positioned to face the back surface of the semiconductor chip; a front-side connecting portion which electrically connects the front electrode and the front-side penetrating electrode; and a back-side connecting portion which electrically connects the back electrode and the back-side penetrating electrode.

Abstract translation: 根据实施例的半导体封装包括：半导体芯片，其前表面包括前电极，背面具有背电极; 在半导体芯片和前侧盖部分之间的部分中包括气隙的前侧盖部分和前侧穿透电极，并且被定位成面向半导体芯片的前表面; 与第一帽部接合以密封半导体芯片的背面盖部分至少在半导体芯片和背面侧帽部分之间的部分和背面贯通电极之间包括气隙，并且位于 面对半导体芯片的背面; 电连接前电极和前侧穿透电极的前侧连接部; 以及将背面电极和背面贯通电极电连接的背面侧连接部。

公开(公告)号：US08419497B2

公开(公告)日：2013-04-16

申请号：US12923949

申请日：2010-10-15

Applicant: Isao Takasu ,  Yuko Nomura ,  Tsuyoshi Hioki ,  Isao Amemiya ,  Kazuhide Abe

Inventor： Isao Takasu ,  Yuko Nomura ,  Tsuyoshi Hioki ,  Isao Amemiya ,  Kazuhide Abe

IPC: H01J9/00

CPC classification number: H01L33/54 ,  H01L33/46 ,  H01L33/507 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2933/0041 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method of manufacturing a light emitting device. The method includes: mounting a light emitting chip on a substrate; forming a transparent resin portion and a phosphor layer by using a liquid droplet discharging apparatus, the transparent resin portion being formed in a shape of a dome and covering the light emitting chip to fill an exterior thereof on the substrate, a phosphor layer containing phosphor and being formed on an exterior of the transparent resin portion close to at least a top side thereof; and forming a reflecting layer at a position exterior of the transparent resin portion and the phosphor layer close to the substrate.

Abstract translation: 一种制造发光器件的方法。 该方法包括：将发光芯片安装在基板上; 通过使用液滴喷射装置形成透明树脂部分和荧光体层，所述透明树脂部分形成为圆顶形状并且覆盖所述发光芯片以将其外部填充在所述基板上，所述荧光体层包含磷光体和 形成在透明树脂部分的至少其顶侧附近的外部; 并且在透明树脂部分的外部和靠近基板的荧光体层的位置处形成反射层。

公开(公告)号：US20120228755A1

公开(公告)日：2012-09-13

申请号：US13235386

申请日：2011-09-18

Applicant: Toshihiko NAGANO ,  Hiroshi Yamada ,  Kazuhide Abe ,  Kazuhiko Itaya ,  Taihei Nakada

Inventor： Toshihiko NAGANO ,  Hiroshi Yamada ,  Kazuhide Abe ,  Kazuhiko Itaya ,  Taihei Nakada

IPC: H01L23/053 ,  H01L21/56

CPC classification number: H01L23/04 ,  H01L23/13 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00

Abstract: A semiconductor module includes a high frequency chip, an insulating cap, a through electrode, interconnections, and an insulating layer. The insulating cap forms a hollow with the chip to cover the chip. The through electrode passes through a first plane of the cap and a second plane of the cap, the first plane facing the chip, the second plane being on a side opposite to the first plane. The interconnections are provided on the cap and connected to the through electrode. The insulating layer is provided on the cap and fills a portion between the interconnections therewith.

Abstract translation: 半导体模块包括高频芯片，绝缘帽，通孔，互连和绝缘层。 绝缘盖形成具有芯片的中空以覆盖芯片。 所述贯通电极通过所述盖的第一平面和所述盖的第二平面，所述第一平面面向所述芯片，所述第二平面位于与所述第一平面相对的一侧。 互连设置在盖上并连接到通孔。 绝缘层设置在盖上并填充与其互连之间的部分。