公开(公告)号：US20230260866A1

公开(公告)日：2023-08-17

申请号：US18157159

申请日：2023-01-20

Applicant: MEDIATEK INC.

Inventor： Yin-Fa CHEN ,  Bo-Jiun YANG ,  Ta-Jen YU ,  Bo-Hao MA ,  Chih-Wei CHANG ,  Tsung-Yu PAN ,  Tai-Yu CHEN ,  Shih-Chin LIN ,  Wen-Sung HSU

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/498 ,  H01L23/13

CPC classification number: H01L23/3675 ,  H01L24/73 ,  H01L24/16 ,  H01L24/32 ,  H01L24/17 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/13 ,  H01L2924/1511 ,  H01L2924/15151 ,  H01L2924/152 ,  H01L2924/15331 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/32059 ,  H01L2224/32225 ,  H01L2224/17051 ,  H01L2924/1011

Abstract: A semiconductor package structure includes a package substrate, a semiconductor die, an interposer, an adhesive layer, and a molding material. The semiconductor die is disposed over the package substrate. The interposer is disposed over the semiconductor die. The adhesive layer connects the semiconductor die and the interposer. The molding material surrounds the semiconductor die and the adhesive layer.

公开(公告)号：US20180233474A1

公开(公告)日：2018-08-16

申请号：US15881063

申请日：2018-01-26

Applicant: MEDIATEK INC.

Inventor： Ta-Jen YU ,  Chi-Yuan CHEN ,  Wen-Sung HSU

IPC: H01L23/00

Abstract: The invention provides a semiconductor package. The semiconductor package includes a semiconductor die and a conductive pillar bump structure and a conductive plug. The semiconductor die has a die pad thereon. The conductive pillar bump structure is positioned overlying the die pad. The conductive pillar bump structure includes an under bump metallurgy (UBM) stack having a first diameter and a conductive plug on the UBM stack. The conductive plug has a second diameter that is different than the first diameter.

公开(公告)号：US20170186709A1

公开(公告)日：2017-06-29

申请号：US15455200

申请日：2017-03-10

Applicant: MediaTek Inc.

Inventor： Wen-Sung HSU ,  Ta-Jen YU

IPC: H01L23/64 ,  H01L23/498 ,  H05K3/00 ,  H01L21/48 ,  H05K3/32 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/5384 ,  H01L2224/16227 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/185 ,  H05K3/205 ,  H01L2924/00012 ,  H01L2924/0001

Abstract: A manufacturing method of a package substrate is provided. The method includes forming a first circuit layer on a carrier. A passive component is disposed on the first circuit layer and the carrier. A dielectric layer is formed on the carrier to embed the passive component and the first circuit layer in the dielectric layer. A second circuit layer is formed on the dielectric layer. The carrier is removed from the dielectric layer. A manufacturing method of a chip package is also provided.

公开(公告)号：US20150262840A1

公开(公告)日：2015-09-17

申请号：US14663772

申请日：2015-03-20

Applicant: MediaTek Inc

Inventor： Wen-Sung HSU ,  Ta-Jen YU

IPC: H01L21/48 ,  H01L23/498

CPC classification number: H01L21/485 ,  H01F17/00 ,  H01F17/0006 ,  H01L21/486 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/705 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/642 ,  H01L23/645 ,  H01L23/66 ,  H01L24/17 ,  H01L25/50 ,  H01L2224/13147 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2924/12042 ,  H01L2924/1206 ,  H01L2924/1421 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/2064 ,  H05K1/165 ,  H05K1/181 ,  H05K1/183 ,  H05K3/0017 ,  H05K3/0026 ,  H05K3/0047 ,  H05K3/107 ,  H05K3/188 ,  H05K3/303 ,  H05K2201/10098 ,  H01L2924/00

Abstract: A method for fabricating a base for a semiconductor package is provided. The method operates by providing a carrier with conductive seed layers on the top surface and the bottom surface of the carrier, forming radio-frequency (RF) devices respectively on the conductive seed layers, laminating a first base material layer and a second base material layer respectively on the conductive seed layers, covering the RF devices, and separating the first base material layer the second base material layer, which contain the RF devices thereon, from the carrier to form a first base and a second base.

Abstract translation: 提供了一种制造用于半导体封装的基座的方法。 该方法通过在载体的顶表面和底表面上提供具有导电种子层的载体来工作，分别在导电种子层上形成射频（RF）装置，层压第一基材层和第二基材层 分别在导电种子层上覆盖RF器件，以及将第一基底层与载体上包含RF器件的第二基底层分离，形成第一基底和第二基底。

公开(公告)号：US20140151867A1

公开(公告)日：2014-06-05

申请号：US14173976

申请日：2014-02-06

Applicant: MediaTek Inc.

Inventor： Tzu-Hung LIN ,  Wen-Sung HSU ,  Ta-Jen YU ,  Andrew C. CHANG

IPC: H01L23/495

Abstract: The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure.

Abstract translation: 本发明提供半导体封装和用于制造用于半导体封装的基座的方法。 半导体封装包括嵌入基座中的导电迹线。 半导体器件通过导电结构安装在导电迹线上。

公开(公告)号：US20180233425A1

公开(公告)日：2018-08-16

申请号：US15881030

申请日：2018-01-26

Applicant: MEDIATEK INC.

Inventor： Ta-Jen YU ,  Wen-Sung HSU

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/683

CPC classification number: H01L23/3114 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/562 ,  H01L24/02 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0231 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121

Abstract: The invention provides a semiconductor package and a method for fabricating the same. The semiconductor package includes a redistribution layer (RDL) structure, a semiconductor die, a molding compound and a supporter. The RDL structure has a first surface and a second surface opposite to the first surface. The semiconductor die is disposed on the first surface of the RDL structure and electrically coupled to the RDL structure. The molding compound is positioned overlying the semiconductor die and the first surface of the RDL structure. The supporter is positioned beside the semiconductor die and in contact with the first surface of the RDL structure.

公开(公告)号：US20170186676A1

公开(公告)日：2017-06-29

申请号：US15460583

申请日：2017-03-16

Applicant: MEDIATEK, INC.

Inventor： Wen-Sung HSU ,  Tzu-Hung LIN ,  Ta-Jen YU

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/49811 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/3171 ,  H01L23/3178 ,  H01L23/3192 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/26 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/02331 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81385 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package is provided. In one configuration, the semiconductor package includes a substrate having a die attach surface. A conductive trace is disposed on the substrate, wherein the conductive trace is elongated and carries a signal or a ground across at least a portion of the substrate. A die is mounted on the die attach surface of the substrate via a conductive pillar bump, the conductive pillar bump being rounded and elongated such that the conductive pillar bump extends along a length of the conductive trace and contacts the conductive trace at an end or at an intermediate portion thereof. The die further includes a metal pad electrically coupling to the conductive pillar bump, wherein the metal pad has a first edge and a second edge substantially vertical to the first edge, and wherein the first edge is not adjacent to the second edge.

公开(公告)号：US20160219714A1

公开(公告)日：2016-07-28

申请号：US14602539

申请日：2015-01-22

Applicant: MediaTek Inc.

Inventor： Wen-Sung HSU ,  Ta-Jen YU

IPC: H05K1/18 ,  H01L21/48 ,  H05K3/00 ,  H05K3/32 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/5384 ,  H01L2224/16227 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/185 ,  H05K3/205 ,  H01L2924/00012 ,  H01L2924/0001

Abstract: A package substrate is provided. The package substrate includes: a dielectric layer; a passive component embedded in the dielectric layer and contacting the dielectric layer; and a circuit layer embedded in the dielectric layer and having a first surface aligned with a second surface of the dielectric layer.

Abstract translation: 提供封装基板。 封装基板包括：电介质层; 嵌入在介电层中并与电介质层接触的无源元件; 以及电介质层，其电介质层具有与介电层的第二表面对准的第一表面。

公开(公告)号：US20160133594A1

公开(公告)日：2016-05-12

申请号：US14535643

申请日：2014-11-07

Applicant: MediaTek Inc.

Inventor： Ching-Liou HUANG ,  Ta-Jen YU

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/17 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3192 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L2221/68345 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/05022 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16105 ,  H01L2224/16235 ,  H01L2224/17104 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32221 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: The invention provides a semiconductor package. The semiconductor package includes a base having a device-attach surface and a solder-ball attach surface opposite to the device-attach surface. A conductive via is disposed passing through the base. The conductive via includes a first terminal surface aligned to the device-attach surface of the base. A semiconductor die is mounted on the base by a conductive structure. The conductive structure is in contact with the first terminal surface of the conductive via.

Abstract translation: 本发明提供一种半导体封装。 半导体封装包括具有与器件附着表面相对的器件附着表面和焊球附着表面的基座。 导电通孔设置穿过基座。 导电通孔包括与基座的装置附接表面对准的第一端子表面。 半导体管芯通过导电结构安装在基座上。 导电结构与导电通孔的第一端子表面接触。

公开(公告)号：US20160111358A1

公开(公告)日：2016-04-21

申请号：US14980445

申请日：2015-12-28

Applicant: MediaTek Inc.

Inventor： Wen-Sung HSU ,  Tzu-Hung LIN ,  Ta-Jen YU

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49811 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/3171 ,  H01L23/3178 ,  H01L23/3192 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/26 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/02331 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81385 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package is provided. In one configuration, the semiconductor package includes a substrate. First and second conductive traces are disposed on the substrate. A conductive pillar bump is disposed on the second conductive trace, and a first conductive structure is disposed between the second conductive trace and the conductive pillar bump or between the second conductive trace and the substrate. A semiconductor die is disposed over the first conductive trace, wherein the conductive pillar bump connects to the semiconductor die.

Abstract translation: 提供半导体封装。 在一种配置中，半导体封装包括衬底。 第一和第二导电迹线设置在基板上。 导电柱突起设置在第二导电迹线上，并且第一导电结构设置在第二导电迹线和导电柱突起之间或第二导电迹线和基底之间。 半导体管芯设置在第一导电迹线上，其中导电柱凸块连接到半导体管芯。