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    Methods of forming line patterns in substrates
    11.
    发明授权
    Methods of forming line patterns in substrates 有权
    在基板上形成线图案的方法

    公开(公告)号：US09330914B2

    公开(公告)日：2016-05-03

    申请号：US14049135

    申请日：2013-10-08

    Applicant: Micron Technology, Inc.

    Inventor： Scott L. Light ,  Vishal Sipani ,  Michael D. Hyatt

    IPC: H01L21/311 ,  H01L21/033

    CPC classification number: H01L21/0337

    Abstract: A method including forming a line pattern in a substrate includes using a plurality of longitudinally spaced projecting features formed along respective guide lines as a template in forming a plurality of directed self-assembled (DSA) lines that individually comprise at least one of (a): the spaced projecting features and DSA material longitudinally there-between, and (b): are laterally between and laterally spaced from immediately adjacent of the guide lines. Substrate material elevationally inward of and laterally between the DSA lines may be processed using the DSA lines as a mask.

    Abstract translation: 包括在衬底中形成线图案的方法包括在形成多个定向自组装（DSA）线时使用沿着相应引导线形成的多个纵向间隔开的突出特征作为模板，所述定向自组装（DSA）线分别包括以下中的至少一个：（a） ：在其间纵向延伸的间隔开的突出特征和DSA材料，和（b）之间：在紧邻引导线之间横向间隔开并且横向间隔开。 可以使用DSA线作为掩模来处理DSA线之间和横向上的基底材料。

    METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS
    13.
    发明公开
    METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS 审中-公开

    公开(公告)号：US20240349478A1

    公开(公告)日：2024-10-17

    申请号：US18619000

    申请日：2024-03-27

    Applicant: Micron Technology, Inc.

    Inventor： Fatma Arzum Simsek-Ege ,  Scott L. Light ,  Efe S. Ege ,  Chunhua Yao

    IPC: H10B12/00

    CPC classification number: H10B12/0335 ,  H10B12/315 ,  H10B12/482 ,  H10B12/485

    Abstract: A method of forming a microelectronic device includes forming a first dielectric stack over a semiconductor base structure including pillar structures separated by filled isolation trenches. Digit line contacts are formed to partially vertically extend through the first dielectric stack and into digit line contact regions of the pillar structures. Digit lines are formed over and in contact with the digit line contacts, and partially vertically extend through the first dielectric stack. A second dielectric stack is formed over the digit lines and the first dielectric stack. Storage node contacts are formed to vertically extend partially through the second dielectric stack, completely through the first dielectric stack, and into storage node contact regions of the pillar structures. Redistribution layer structures are formed over and in contact with the storage node contacts, and partially vertically extend through the second dielectric stack. Microelectronic devices, memory devices, and electronic systems are also described.

    Lithography methods, methods for forming patterning tools and patterning tools
    15.
    发明授权
    Lithography methods, methods for forming patterning tools and patterning tools 有权
    平版印刷方法，图案形成工具和图形工具的形成方法

    公开(公告)号：US09176385B2

    公开(公告)日：2015-11-03

    申请号：US14107767

    申请日：2013-12-16

    Applicant: Micron Technology, Inc.

    Inventor： Jianming Zhou ,  Scott L. Light ,  David Kewley ,  Prasanna Srinivasan ,  Anton deVilliers

    IPC: G03F1/44 ,  G03F7/20 ,  G03F1/26 ,  G03F1/32

    CPC classification number: G03F7/20 ,  G03F1/26 ,  G03F1/32 ,  G03F7/70433 ,  G03F7/70883

    Abstract: Methods of lithography, methods for forming patterning tools, and patterning tools are described. One such patterning tool include an active region that forms a first diffraction image on a lens when in use, and an inactive region that forms a second diffraction image on a lens when in use. The inactive region includes a pattern of phase shifting features formed in a substantially transparent material of the patterning tool. Patterning tools and methods, as described, can be used to compensate for lens distortion from effects such as localized heating.

    Abstract translation: 描述了光刻方法，用于形成图案形成工具的方法和图案形成工具。 一种这样的图案形成工具包括在使用时在透镜上形成第一衍射图像的有源区域和在使用时在透镜上形成第二衍射图像的非活性区域。 非活性区域包括形成在图案形成工具的基本上透明的材料中的相移特征的图案。 如所描述的图案化工具和方法可用于补偿透镜失真，例如局部加热等影响。

    METHODS FOR FORMING SUB-RESOLUTION FEATURES IN SEMICONDUCTOR DEVICES
    16.
    发明申请
    METHODS FOR FORMING SUB-RESOLUTION FEATURES IN SEMICONDUCTOR DEVICES 有权
    在半导体器件中形成分解特征的方法

    公开(公告)号：US20140370684A1

    公开(公告)日：2014-12-18

    申请号：US13918065

    申请日：2013-06-14

    Applicant: Micron Technology, Inc.

    Inventor： Ranjan Khurana ,  Michael Hyatt ,  Scott L. Light ,  Kevin J. Torek ,  Anton J. deVilliers

    IPC: H01L21/768 ,  H01L49/02

    CPC classification number: H01L21/76816 ,  G03F7/0035 ,  G03F7/095 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L28/90

    Abstract: Methods of forming semiconductor devices and features in semiconductor device structures include conducting an anti-spacer process to remove portions of a first mask material to form first openings extending in a first direction. Another anti-spacer process is conducted to remove portions of the first mask material to form second openings extending in a second direction at an angle to the first direction. Portions of the second mask material underlying the first mask material at intersections of the first openings and second openings are removed to form holes in the second mask material and to expose a substrate underlying the second mask material.

    Abstract translation: 在半导体器件结构中形成半导体器件和特征的方法包括进行防间隔工艺以去除第一掩模材料的部分以形成沿第一方向延伸的第一开口。 进行另一个防间隔处理以去除第一掩模材料的部分，以形成沿与第一方向成角度的第二方向延伸的第二开口。 去除在第一开口和第二开口的交叉点处的第一掩模材料下面的第二掩模材料的部分，以在第二掩模材料中形成孔并暴露第二掩模材料下面的衬底。

    LITHOGRAPHY WAVE-FRONT CONTROL SYSTEM AND METHOD
    18.
    发明申请
    LITHOGRAPHY WAVE-FRONT CONTROL SYSTEM AND METHOD 审中-公开
    LITHOGRAPHY波前控制系统和方法

    公开(公告)号：US20140247476A1

    公开(公告)日：2014-09-04

    申请号：US14277323

    申请日：2014-05-14

    Applicant: Micron Technology, Inc.

    Inventor： Yuan He ,  Jianming Zhou ,  Scott L. Light ,  Anton deVilliers ,  Kaveri Jain ,  Zishu Zhang ,  Dan Millward

    IPC: G02B26/06

    CPC classification number: G02B26/06 ,  G03F7/70091 ,  G03F7/70125 ,  G03F7/70258 ,  G03F7/70308 ,  G03F7/705 ,  G03F7/706

    Abstract: Some embodiments include system and methods to obtain information for adjusting variations in features formed on a substrate of a semiconductor device. Such methods can include determining a first pupil in an illumination system used to form a first feature, and determining a second pupil used to form a second feature. The methods can also include determining a pupil portion belonging to only one of the pupils, and generating a modified pupil portion from the pupil portion. Information associated with the modified pupil portion can be obtained for controlling a portion of a projection lens assembly of an illumination system. Other embodiments are described.

    Abstract translation: 一些实施例包括用于获得用于调整形成在半导体器件的衬底上的特征的变化的信息的系统和方法。 这样的方法可以包括确定用于形成第一特征的照明系统中的第一光瞳，以及确定用于形成第二特征的第二光瞳。 所述方法还可以包括确定属于仅一个瞳孔的瞳孔部分，并且从瞳孔部分产生修改的瞳孔部分。 可以获得与修改的瞳孔部分相关联的信息，用于控制照明系统的投影透镜组件的一部分。 描述其他实施例。

    Semiconductor constructions and methods of forming patterns
    19.
    发明授权
    Semiconductor constructions and methods of forming patterns 有权
    半导体结构和形成图案的方法

    公开(公告)号：US08815497B2

    公开(公告)日：2014-08-26

    申请号：US13941747

    申请日：2013-07-15

    Applicant: Micron Technology, Inc.

    Inventor： Dan Millward ,  Kaveri Jain ,  Zishu Zhang ,  Lijing Gou ,  Anton J. deVillers ,  Jianming Zhou ,  Yuan He ,  Michael Hyatt ,  Scott L. Light

    IPC: G03F7/26

    CPC classification number: H01L21/76879 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10882 ,  H01L27/10888

    Abstract: Some embodiments include methods of forming patterns. A semiconductor substrate is formed to comprise an electrically insulative material over a set of electrically conductive structures. An interconnect region is defined across the electrically conductive structures, and regions on opposing sides of the interconnect region are defined as secondary regions. A two-dimensional array of features is formed over the electrically insulative material. The two-dimensional array extends across the interconnect region and across the secondary regions. A pattern of the two-dimensional array is transferred through the electrically insulative material of the interconnect region to form contact openings that extend through the electrically insulative material and to the electrically conductive structures, and no portions of the two-dimensional array of the secondary regions is transferred into the electrically insulative material.

    Abstract translation: 一些实施例包括形成图案的方法。 半导体衬底被形成为在一组导电结构之上包括电绝缘材料。 跨导电结构限定互连区域，并且互连区域的相对侧上的区域被定义为次级区域。 特征的二维阵列形成在电绝缘材料上。 二维阵列跨越互连区域并跨越次级区域延伸。 二维阵列的图案通过互连区域的电绝缘材料转移以形成延伸穿过电绝缘材料和导电结构的接触开口，并且二次区域的二维阵列的任何部分 被转移到电绝缘材料中。

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