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27 条记录 (耗时 0.016 秒)

    Coreless substrate and method for making the same
    11.
    发明授权
    Coreless substrate and method for making the same 有权
    无芯底物和制造方法

    公开(公告)号：US08416577B2

    公开(公告)日：2013-04-09

    申请号：US12691502

    申请日：2010-01-21

    申请人： Chien-Hao Wang ,  Ming-Chiang Lee

    发明人： Chien-Hao Wang ,  Ming-Chiang Lee

    IPC分类号： H05K1/00

    CPC分类号： H05K3/4007 ,  H05K1/111 ,  H05K1/113 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0097 ,  H05K3/06 ,  H05K3/108 ,  H05K3/205 ,  H05K3/28 ,  H05K3/385 ,  H05K3/4682 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2203/0315

    摘要： The present invention relates to a coreless substrate and a method for making the same. The method for making the coreless substrate includes: (a) providing a carrier and a first conductive layer, wherein the carrier has a first surface and a second surface, and the first conductive layer is disposed on the first surface of the carrier; (b) forming a first embedded circuit on the first conductive layer; (c) forming a first dielectric layer so as to cover the first embedded circuit; (d) removing the carrier; (e) removing part of the first conductive layer so as to form at least one first pad; and (f) forming a first solder mask so as to cover the first embedded circuit and the first dielectric layer and to expose the first pad. Therefore, the coreless substrate of the present invention has high density of layout and involves low manufacturing cost.

    摘要翻译： 无芯基板及其制造方法技术领域本发明涉及无芯基板及其制造方法。 制造无芯基板的方法包括：（a）提供载体和第一导电层，其中载体具有第一表面和第二表面，并且第一导电层设置在载体的第一表面上; （b）在第一导电层上形成第一嵌入电路; （c）形成第一介电层以覆盖第一嵌入式电路; （d）清除载体; （e）去除所述第一导电层的一部分以便形成至少一个第一焊盘; 和（f）形成第一焊料掩模以覆盖第一嵌入电路和第一电介质层并露出第一焊盘。 因此，本发明的无芯基板具有高的布局密度，并且制造成本低。

    CHIP PACKAGE
    13.
    发明申请
    CHIP PACKAGE 有权
    芯片包装

    公开(公告)号：US20110260327A1

    公开(公告)日：2011-10-27

    申请号：US13173255

    申请日：2011-06-30

    申请人： Ming-Chiang Lee

    发明人： Ming-Chiang Lee

    IPC分类号： H01L23/48

    CPC分类号： H01L21/568 ,  H01L23/3107 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2924/181 ,  H01L2924/00012

    摘要： A quad flat non-leaded package including a first patterned conductive layer, a second patterned conductive layer, a chip, bonding wires and a molding compound is provided. The first patterned conductive layer defines a first space, and the second patterned conductive layer defines a second space, wherein the first space overlaps the second space and a part of the second patterned conductive layer surrounding the second space. The chip is disposed on the second patterned conductive layer. The bonding wires are connected between the chip and the second patterned conductive layer. The molding compound encapsulates the second patterned conductive layers, the chip and the bonding wires. In addition, a method of manufacturing a quad flat non-leaded package is also provided.

    摘要翻译： 提供了包括第一图案化导电层，第二图案化导电层，芯片，接合线和模制化合物的四边形扁平非引线封装。 第一图案化导电层限定第一空间，并且第二图案化导电层限定第二空间，其中第一空间与第二空间重叠，并且第二图案化导电层的一部分围绕第二空间。 芯片设置在第二图案化导电层上。 接合线连接在芯片和第二图案化导电层之间。 模制化合物封装第二图案化导电层，芯片和接合线。 此外，还提供了制造四边形非铅包装的方法。

    STRUCTURE HAVING MULTI-TRACE VIA SUBSTRATE AND METHOD OF FABRICATING THE SAME
    14.
    发明申请
    STRUCTURE HAVING MULTI-TRACE VIA SUBSTRATE AND METHOD OF FABRICATING THE SAME 有权
    具有基底的多层结构的结构及其制造方法

    公开(公告)号：US20110174529A1

    公开(公告)日：2011-07-21

    申请号：US12790417

    申请日：2010-05-28

    申请人： Min-Yao CHEN ,  Mao-Chang Chuang ,  Ming-Chiang Lee ,  Chien-Hao Wang

    发明人： Min-Yao CHEN ,  Mao-Chang Chuang ,  Ming-Chiang Lee ,  Chien-Hao Wang

    IPC分类号： H05K1/11 ,  G03F7/20 ,  C25D5/02

    CPC分类号： H05K3/403 ,  C25D5/022 ,  H05K3/108 ,  H05K2201/09645 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49165

    摘要： A method of fabricating a multi-trace via substrate is disclosed. A substrate at least having a first surface and a hole is provided, wherein the hole has a hole wall. A first conductive layer is formed on the entire surface of the substrate and the hole wall. A photoresist layer applied over the entire surface of the first conductive layer is selectively patterned to define a plurality of laterally separated regions on the first conductive layer. A patterned photoresist layer is used as a mask and a second conductive layer substantially thicker than the first conductive layer is electroplated on the laterally separated regions. The patterned photoresist layer is removed. The portion of the first conductive layer not covered by the second conductive layer is substantially removed to form a plurality of laterally separated traces extended on the first surface and through the hole.

    摘要翻译： 公开了一种制造多迹线通孔衬底的方法。 提供至少具有第一表面和孔的基底，其中孔具有孔壁。 在基板的整个表面和孔壁上形成第一导电层。 施加在第一导电层的整个表面上的光致抗蚀剂层被选择性地图案化以在第一导电层上限定多个横向分离的区域。 使用图案化的光致抗蚀剂层作为掩模，并且基本上比第一导电层厚的第二导电层电镀在横向分离的区域上。 去除图案化的光致抗蚀剂层。 未被第二导电层覆盖的第一导电层的部分被基本上去除，以形成在第一表面上延伸并穿过孔的多个横向分离的迹线。