公开(公告)号：US08372689B2

公开(公告)日：2013-02-12

申请号：US12691660

申请日：2010-01-21

申请人： Ming-Chiang Lee ,  Chien-Hao Wang

发明人： Ming-Chiang Lee ,  Chien-Hao Wang

IPC分类号： H01L21/00

CPC分类号： H01L23/5389 ,  H01L21/4846 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/82

摘要： In one embodiment, a method of forming a semiconductor device package includes: (1) providing a carrier and a semiconductor device including an active surface; (2) forming a first redistribution structure including a first electrical interconnect extending laterally within the first structure and a plurality of second electrical interconnects extending vertically from a first surface of the first interconnect, each second interconnect including a lower surface adjacent to the first surface and an upper surface opposite the lower surface; (3) disposing the device on the carrier such that the active surface is adjacent to the carrier; (4) disposing the first structure on the carrier such that the upper surface of each second interconnect is adjacent to the carrier, and the second interconnects are positioned around the device; and (5) forming a second redistribution structure adjacent to the active surface, and including a third electrical interconnect extending laterally within the second structure.

摘要翻译： 在一个实施例中，形成半导体器件封装的方法包括：（1）提供载体和包括活性表面的半导体器件; （2）形成第一再分配结构，其包括在第一结构内横向延伸的第一电互连和从第一互连的第一表面垂直延伸的多个第二电互连，每个第二互连包括与第一表面相邻的下表面， 与下表面相对的上表面; （3）将所述装置设置在所述载体上使得所述活性表面与所述载体相邻; （4）将所述第一结构设置在所述载体上，使得每个第二互连件的上表面与所述载体相邻，并且所述第二互连件围绕所述装置定位; 和（5）形成与活性表面相邻的第二再分布结构，并且包括在第二结构内横向延伸的第三电互连。

公开(公告)号：US08288869B2

公开(公告)日：2012-10-16

申请号：US12779818

申请日：2010-05-13

申请人： Shih-Fu Huang ,  Yuan-Chang Su ,  Chia-Cheng Chen ,  Kuang-Hsiung Chen ,  Ming-Chiang Lee ,  Bernd Karl Appelt ,  Chia-Hsiung Hsieh

发明人： Shih-Fu Huang ,  Yuan-Chang Su ,  Chia-Cheng Chen ,  Kuang-Hsiung Chen ,  Ming-Chiang Lee ,  Bernd Karl Appelt ,  Chia-Hsiung Hsieh

IPC分类号： H01L23/48

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L23/145 ,  H01L24/16 ,  H01L24/28 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/13099 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A semiconductor package includes a substrate, a die, and a package body. The substrate includes: (a) a core including a resin reinforced with fibers; (b) a plurality of openings extending through the core; (c) a dielectric layer; and (d) a single conductive layer disposed between the dielectric layer and the core. Portions of a lower surface of the single conductive layer cover the plurality of openings to form a plurality of first contact pads for electrical connection external to the semiconductor package. Exposed portions of an upper surface of the single conductive layer form a plurality of second contact pads. The die is electrically connected to the plurality of second contact pads, and the package body encapsulates the die.

摘要翻译： 半导体封装包括基板，管芯和封装体。 基材包括：（a）包含用纤维增强的树脂的芯; （b）延伸穿过所述芯的多个开口; （c）电介质层; 和（d）设置在电介质层和芯之间的单个导电层。 单个导电层的下表面的一部分覆盖多个开口以形成多个用于半导体封装外部电连接的第一接触焊盘。 单个导电层的上表面的暴露部分形成多个第二接触焊盘。 模具电连接到多个第二接触焊盘，并且封装体封装模具。

公开(公告)号：US20100206618A1

公开(公告)日：2010-08-19

申请号：US12691502

申请日：2010-01-21

申请人： Chien-Hao Wang ,  Ming-Chiang Lee

发明人： Chien-Hao Wang ,  Ming-Chiang Lee

IPC分类号： H05K1/09 ,  H05K3/00 ,  C23C28/00

CPC分类号： H05K3/4007 ,  H05K1/111 ,  H05K1/113 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0097 ,  H05K3/06 ,  H05K3/108 ,  H05K3/205 ,  H05K3/28 ,  H05K3/385 ,  H05K3/4682 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2203/0315

摘要： The present invention relates to a coreless substrate and a method for making the same. The method for making the coreless substrate includes: (a) providing a carrier and a first conductive layer, wherein the carrier has a first surface and a second surface, and the first conductive layer is disposed on the first surface of the carrier; (b) forming a first embedded circuit on the first conductive layer; (c) forming a first dielectric layer so as to cover the first embedded circuit; (d) removing the carrier; (e) removing part of the first conductive layer so as to form at least one first pad; and (f) forming a first solder mask so as to cover the first embedded circuit and the first dielectric layer and to expose the first pad. Therefore, the coreless substrate of the present invention has high density of layout and involves low manufacturing cost.

摘要翻译： 无芯基板及其制造方法技术领域本发明涉及无芯基板及其制造方法。 制造无芯基板的方法包括：（a）提供载体和第一导电层，其中载体具有第一表面和第二表面，并且第一导电层设置在载体的第一表面上; （b）在第一导电层上形成第一嵌入电路; （c）形成第一介电层以覆盖第一嵌入式电路; （d）清除载体; （e）去除所述第一导电层的一部分以便形成至少一个第一焊盘; 和（f）形成第一焊料掩模以覆盖第一嵌入电路和第一电介质层并露出第一焊盘。 因此，本发明的无芯基板具有高的布局密度，并且制造成本低。

公开(公告)号：US08497585B2

公开(公告)日：2013-07-30

申请号：US13173255

申请日：2011-06-30

申请人： Ming-Chiang Lee

发明人： Ming-Chiang Lee

IPC分类号： H01L23/48 ,  H01L23/28

CPC分类号： H01L21/568 ,  H01L23/3107 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2924/181 ,  H01L2924/00012

摘要： A quad flat non-leaded package including a first patterned conductive layer, a second patterned conductive layer, a chip, bonding wires and a molding compound is provided. The first patterned conductive layer defines a first space, and the second patterned conductive layer defines a second space, wherein the first space overlaps the second space and a part of the second patterned conductive layer surrounding the second space. The chip is disposed on the second patterned conductive layer. The bonding wires are connected between the chip and the second patterned conductive layer. The molding compound encapsulates the second patterned conductive layers, the chip and the bonding wires. In addition, a method of manufacturing a quad flat non-leaded package is also provided.

摘要翻译： 提供了包括第一图案化导电层，第二图案化导电层，芯片，接合线和模制化合物的四边形扁平非引线封装。 第一图案化导电层限定第一空间，并且第二图案化导电层限定第二空间，其中第一空间与第二空间重叠，并且第二图案化导电层的一部分围绕第二空间。 芯片设置在第二图案化导电层上。 接合线连接在芯片和第二图案化导电层之间。 模制化合物封装第二图案化导电层，芯片和接合线。 此外，还提供了制造四边形非铅包装的方法。

公开(公告)号：US08387239B2

公开(公告)日：2013-03-05

申请号：US12622052

申请日：2009-11-19

申请人： Chien-Hao Wang ,  Ming-Chiang Lee

发明人： Chien-Hao Wang ,  Ming-Chiang Lee

IPC分类号： H05K3/02 ,  H05K3/10

CPC分类号： H05K3/4658 ,  H05K3/0097 ,  H05K3/205 ,  H05K3/28 ,  H05K3/4602 ,  H05K3/462 ,  H05K3/4647 ,  H05K2201/09563 ,  H05K2203/063 ,  H05K2203/0733 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155

摘要： An embedded circuit substrate comprising: a core structure having a first surface and a second surface opposite to each other; a first patterned conductive layer disposed on the first surface and embedded in the core structure; a second patterned conductive layer disposed on the second surface and embedded in the core structure; and a plurality of conductive blocks disposed in the core structure for conducting the first patterned conductive layer and the second patterned conductive layer is provided. Furthermore, a manufacturing method of an embedded circuit substrate is also provided.

摘要翻译： 一种嵌入式电路基板，包括：具有彼此相对的第一表面和第二表面的芯结构; 布置在所述第一表面上并嵌入所述芯结构中的第一图案化导电层; 第二图案化导电层，设置在第二表面上并嵌入在芯结构中; 并且设置在芯结构中用于导电第一图案化导电层和第二图案化导电层的多个导电块。 此外，还提供了嵌入式电路基板的制造方法。

公开(公告)号：US08320134B2

公开(公告)日：2012-11-27

申请号：US12701486

申请日：2010-02-05

申请人： Yuan-Chang Su ,  Shih-Fu Huang ,  Ming-Chiang Lee ,  Chien-Hao Wang

发明人： Yuan-Chang Su ,  Shih-Fu Huang ,  Ming-Chiang Lee ,  Chien-Hao Wang

IPC分类号： H05K1/18

CPC分类号： H01L23/5389 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/48 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/3025 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An embodiment of an embedded component substrate includes: (1) a semiconductor device including lower, lateral, and upper surfaces; (2) a first patterned conductive layer including a first electrical interconnect extending substantially laterally within the first patterned conductive layer; (3) a second electrical interconnect extending substantially vertically from a first surface of the first interconnect, and including lateral and upper surfaces, and a lower surface adjacent to the first surface; (4) a dielectric layer including an opening extending from an upper surface of the dielectric layer to a lower surface of the dielectric layer, where: (a) the dielectric layer substantially covers the lateral and upper surfaces of the device, and at least a portion of the lateral surface of the second interconnect; and (b) the second interconnect substantially fills the opening; and (5) a second patterned conductive layer adjacent to the upper surfaces of the dielectric layer and the second interconnect.

摘要翻译： 嵌入式部件基板的一个实施例包括：（1）包括下表面，外表面和上表面的半导体器件; （2）第一图案化导电层，包括在第一图案化导电层内基本横向延伸的第一电互连; （3）从所述第一互连的第一表面大致垂直延伸并且包括侧表面和上表面以及与所述第一表面相邻的下表面延伸的第二电互连; （4）介电层，包括从电介质层的上表面延伸到电介质层的下表面的开口，其中：（a）电介质层基本上覆盖器件的横向和上表面，并且至少一个 第二互连的侧表面的部分; 和（b）第二互连基本上填充开口; 和（5）与电介质层和第二互连件的上表面相邻的第二图案化导电层。

公开(公告)号：US07993982B2

公开(公告)日：2011-08-09

申请号：US12556841

申请日：2009-09-10

申请人： Ming-Chiang Lee

发明人： Ming-Chiang Lee

IPC分类号： H01L21/44 ,  H01L21/48

CPC分类号： H01L21/568 ,  H01L23/3107 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2924/181 ,  H01L2924/00012

摘要： A quad flat non-leaded package including a first patterned conductive layer, a second patterned conductive layer, a chip, bonding wires and a molding compound is provided. The first patterned conductive layer defines a first space, and the second patterned conductive layer defines a second space, wherein the first space overlaps the second space and a part of the second patterned conductive layer surrounding the second space. The chip is disposed on the second patterned conductive layer. The bonding wires are connected between the chip and the second patterned conductive layer. The molding compound encapsulates the second patterned conductive layers, the chip and the bonding wires. In addition, a method of manufacturing a quad flat non-leaded package is also provided.

摘要翻译： 提供了包括第一图案化导电层，第二图案化导电层，芯片，接合线和模制化合物的四边形扁平非引线封装。 第一图案化导电层限定第一空间，并且第二图案化导电层限定第二空间，其中第一空间与第二空间重叠，并且第二图案化导电层的一部分围绕第二空间。 芯片设置在第二图案化导电层上。 接合线连接在芯片和第二图案化导电层之间。 模制化合物封装第二图案化导电层，芯片和接合线。 此外，还提供了制造四边形非铅包装的方法。

公开(公告)号：US20100320610A1

公开(公告)日：2010-12-23

申请号：US12779818

申请日：2010-05-13

申请人： SHIH-FU HUANG ,  Yuan-Chang Su ,  Chia-Cheng Chen ,  Kuang-Hsiung Chen ,  Ming-Chiang Lee ,  Bernd Karl Appelt ,  Chia-Hsiung Hsieh

发明人： SHIH-FU HUANG ,  Yuan-Chang Su ,  Chia-Cheng Chen ,  Kuang-Hsiung Chen ,  Ming-Chiang Lee ,  Bernd Karl Appelt ,  Chia-Hsiung Hsieh

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L23/145 ,  H01L24/16 ,  H01L24/28 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/13099 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A semiconductor package includes a substrate, a die, and a package body. The substrate includes: (a) a core including a resin reinforced with fibers; (b) a plurality of openings extending through the core; (c) a dielectric layer; and (d) a single conductive layer disposed between the dielectric layer and the core. Portions of a lower surface of the single conductive layer cover the plurality of openings to form a plurality of first contact pads for electrical connection external to the semiconductor package. Exposed portions of an upper surface of the single conductive layer form a plurality of second contact pads. The die is electrically connected to the plurality of second contact pads, and the package body encapsulates the die.

摘要翻译： 半导体封装包括基板，管芯和封装体。 基材包括：（a）包含用纤维增强的树脂的芯; （b）延伸穿过所述芯的多个开口; （c）电介质层; 和（d）设置在电介质层和芯之间的单个导电层。 单个导电层的下表面的一部分覆盖多个开口以形成多个用于半导体封装外部电连接的第一接触焊盘。 单个导电层的上表面的暴露部分形成多个第二接触焊盘。 模具电连接到多个第二接触焊盘，并且封装体封装模具。

公开(公告)号：US20090075027A1

公开(公告)日：2009-03-19

申请号：US12183398

申请日：2008-07-31

申请人： Ho-Ming Tong ,  Shin-Hua Chao ,  Ming-Chiang Lee ,  Tai-Yuan Huang ,  Chao-Yuan Liu ,  Yung-Cheng Huang ,  Teck-Chong Lee ,  Jen-Chieh Kao ,  Jau-Shoung Chen

发明人： Ho-Ming Tong ,  Shin-Hua Chao ,  Ming-Chiang Lee ,  Tai-Yuan Huang ,  Chao-Yuan Liu ,  Yung-Cheng Huang ,  Teck-Chong Lee ,  Jen-Chieh Kao ,  Jau-Shoung Chen

IPC分类号： B32B3/24 ,  B32B37/00 ,  B32B38/04 ,  B32B15/04 ,  B32B3/00

CPC分类号： B32B37/226 ,  B32B38/0004 ,  B32B2305/076 ,  B32B2305/342 ,  B32B2311/00 ,  B32B2315/085 ,  B32B2457/00 ,  H01L21/561 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/4334 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/15311 ,  H01L2924/181 ,  Y10T156/10 ,  Y10T156/1052 ,  Y10T428/24331 ,  Y10T428/24612 ,  Y10T428/31678 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A manufacturing process for a thermally enhanced package is disclosed. First, a substrate strip including at least a substrate is provided. Next, at least a chip is disposed on an upper surface of the substrate, and the chip is electrically connected to the substrate. Then, a prepreg and a heat dissipating metal layer are provided, and the heat dissipating metal layer is disposed on a first surface of the prepreg and a second surface of the prepreg faces toward the chip. Finally, the prepreg covers the chip by laminating the prepreg and the substrate.

摘要翻译： 公开了一种用于热增强包装的制造方法。 首先，提供至少包括基板的基板条。 接下来，在基板的上表面上设置至少一个芯片，并且芯片与基板电连接。 然后，设置预浸料和散热金属层，散热金属层设置在预浸料坯的第一表面上，并且预浸料坯的第二表面面向芯片。 最后，预浸料通过层压预浸料和基材覆盖芯片。

公开(公告)号：US08510940B2

公开(公告)日：2013-08-20

申请号：US12790417

申请日：2010-05-28

申请人： Min-Yao Chen ,  Mao-Chang Chuang ,  Ming-Chiang Lee ,  Chien-Hao Wang

发明人： Min-Yao Chen ,  Mao-Chang Chuang ,  Ming-Chiang Lee ,  Chien-Hao Wang

IPC分类号： H01K3/10

CPC分类号： H05K3/403 ,  C25D5/022 ,  H05K3/108 ,  H05K2201/09645 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A method of fabricating a multi-trace via substrate is disclosed. A substrate at least having a first surface and a hole is provided, wherein the hole has a hole wall. A first conductive layer is formed on the entire surface of the substrate and the hole wall. A photoresist layer applied over the entire surface of the first conductive layer is selectively patterned to define a plurality of laterally separated regions on the first conductive layer. A patterned photoresist layer is used as a mask and a second conductive layer substantially thicker than the first conductive layer is electroplated on the laterally separated regions. The patterned photoresist layer is removed. The portion of the first conductive layer not covered by the second conductive layer is substantially removed to form a plurality of laterally separated traces extended on the first surface and through the hole.

摘要翻译： 公开了一种制造多迹线通孔衬底的方法。 提供至少具有第一表面和孔的基底，其中孔具有孔壁。 在基板的整个表面和孔壁上形成第一导电层。 施加在第一导电层的整个表面上的光致抗蚀剂层被选择性地图案化以在第一导电层上限定多个横向分离的区域。 使用图案化的光致抗蚀剂层作为掩模，并且基本上比第一导电层厚的第二导电层电镀在横向分离的区域上。 去除图案化的光致抗蚀剂层。 未被第二导电层覆盖的第一导电层的部分被基本上去除，以形成在第一表面上延伸并穿过孔的多个横向分离的迹线。