公开(公告)号：US20150253121A1

公开(公告)日：2015-09-10

申请号：US14639588

申请日：2015-03-05

Applicant: ROHM CO., LTD.

Inventor： Yuichi NAKAO ,  Yasuhiro FUWA

IPC: G01B7/00 ,  H01L25/16 ,  H01L21/768 ,  H01L43/12 ,  H01L23/31 ,  H01L21/52 ,  H01L43/02 ,  H01L23/528 ,  H01L21/56

CPC classification number: H01L21/52 ,  H01L21/56 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3121 ,  H01L23/49827 ,  H01L25/165 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/15151 ,  H01L2924/15156 ,  H01L2924/15311 ,  H01L2924/15333

Abstract: A semiconductor device is provided with a substrate made of a semiconductor material, an interconnect layer, at least one electronic element, and a sealing resin. The substrate has a main surface and a pair of lateral surfaces that are orthogonal to the main surface and face in opposite directions to each other. A recessed portion that is recessed from the main surface and has an opening portion that opens on at least one of the pair of lateral surfaces is formed in the substrate. The interconnect layer is formed on the substrate. The electronic element is an orientation sensor, for example, and is accommodated in the recessed portion of the substrate. The sealing resin covers the electronic element.

Abstract translation: 半导体器件设置有由半导体材料制成的衬底，互连层，至少一个电子元件和密封树脂。 基板具有与主表面正交并且彼此相反方向面对的主表面和一对侧表面。 在基板上形成有从主表面凹陷并且具有在一对侧面中的至少一个上开口的开口部的凹部。 互连层形成在基板上。 电子元件例如是定向传感器，并且容纳在基板的凹部中。 密封树脂覆盖电子元件。

公开(公告)号：US20150155288A1

公开(公告)日：2015-06-04

申请号：US14615455

申请日：2015-02-06

Applicant: ROHM CO., LTD.

Inventor： Yuichi NAKAO

IPC: H01L27/115 ,  H01L49/02

CPC classification number: H01L27/11507 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/32 ,  H01L21/76849 ,  H01L21/7687 ,  H01L27/11504 ,  H01L28/55 ,  H01L28/57 ,  H01L28/60 ,  H01L28/82

Abstract: A semiconductor-storage-device manufacturing method of the present invention is a method for manufacturing a semiconductor storage device provided with a ferroelectric capacitor including a lower electrode, a ferroelectric film, and an upper electrode, and the method includes a step of embedding a first metal plug and a second metal plug in an insulating layer; a step of forming a covering layer that covers at least the second metal plug while securing a part that comes into electric contact with the first metal plug; a step of forming a deposit structure by sequentially depositing a material for the lower electrode, a material for the ferroelectric film, and a material for the upper electrode after forming the covering layer; and a step of forming the ferroelectric capacitor by etching and removing other parts except a part of the deposit structure such that the part of the deposit structure remains on the first metal plug.

Abstract translation: 本发明的半导体存储元件的制造方法是具有下电极，强电介质膜和上电极的强电介质电容器的半导体存储元件的制造方法，其特征在于，包括： 金属插塞和绝缘层中的第二金属插塞; 形成覆盖层的步骤，所述覆盖层至少覆盖所述第二金属插塞，同时确保与所述第一金属插塞电接触的部分; 在形成覆盖层之后，依次沉积下电极材料，铁电薄膜材料和上电极材料，形成沉积结构的步骤; 以及通过蚀刻除去所述沉积结构的一部分以外的其它部分使得所述沉积结构的所述部分保留在所述第一金属插塞上而形成所述强电介质电容器的步骤。

公开(公告)号：US20150035118A1

公开(公告)日：2015-02-05

申请号：US14516639

申请日：2014-10-17

Applicant: ROHM CO., LTD.

Inventor： Yuichi NAKAO

IPC: H01L27/115 ,  H01L49/02

CPC classification number: H01L27/11507 ,  H01L27/11502 ,  H01L28/55 ,  H01L28/57 ,  H01L28/60 ,  H01L28/65 ,  H01L28/75

Abstract: The semiconductor device according to the present invention includes a ferroelectric film and an electrode stacked on the ferroelectric film. The electrode has a multilayer structure of an electrode lower layer in contact with the ferroelectric film and an electrode upper layer stacked on the electrode lower layer. The electrode upper layer is made of a conductive material having an etching selection ratio with respect to the materials for the ferroelectric film and the electrode lower layer. The upper surface of the electrode upper layer is planarized.

Abstract translation: 根据本发明的半导体器件包括堆叠在强电介质膜上的铁电体膜和电极。 电极具有与铁电体膜接触的电极下层和堆叠在电极下层上的电极上层的多层结构。 电极上层由相对于铁电体膜和电极下层的材料具有蚀刻选择比的导电材料制成。 电极上层的上表面被平坦化。

公开(公告)号：US20240087942A1

公开(公告)日：2024-03-14

申请号：US18512025

申请日：2023-11-17

Applicant: ROHM CO., LTD.

Inventor： Ryosuke YAMADA ,  Yuichi NAKAO

IPC: H01L21/683 ,  H01L21/67 ,  H01L21/687

CPC classification number: H01L21/6836 ,  H01L21/67132 ,  H01L21/68721 ,  H01L2221/68327

Abstract: A method for processing a semiconductor wafer comprises: preparing a semiconductor wafer including a main body and a rim, the rim having a greater thickness than the main body and including a projection projecting; supporting the semiconductor wafer with a holding tape; preparing a base including a stage and an outer portion; setting the semiconductor wafer on the base so that the main body is supported by a support surface of the stage; and separating the main body and the rim by cutting an edge portion of the main body in a state in which the main body is supported by the stage. The setting the semiconductor wafer on the base includes setting the semiconductor wafer on the base so that the main body is supported by the stage in a state in which the projection is separated from a head surface of the outer portion of the base.

公开(公告)号：US20180158696A1

公开(公告)日：2018-06-07

申请号：US15884926

申请日：2018-01-31

Applicant: ROHM CO., LTD.

Inventor： Yuichi NAKAO ,  Yasuhiro FUWA

IPC: H01L21/52 ,  H01L23/31 ,  H01L23/498 ,  H01L23/13 ,  H01L21/56 ,  H01L25/16 ,  H01L23/14

CPC classification number: H01L21/52 ,  H01L21/56 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3121 ,  H01L23/49827 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/165 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15151 ,  H01L2924/15156 ,  H01L2924/15311 ,  H01L2924/15333

Abstract: A semiconductor device is provided with a substrate made of a semiconductor material, an interconnect layer, at least one electronic element, and a sealing resin. The substrate has a main surface and a pair of lateral surfaces that are orthogonal to the main surface and face in opposite directions to each other. A recessed portion that is recessed from the main surface and has an opening portion that opens on at least one of the pair of lateral surfaces is formed in the substrate. The interconnect layer is formed on the substrate. The electronic element is an orientation sensor, for example, and is accommodated in the recessed portion of the substrate. The sealing resin covers the electronic element.

公开(公告)号：US20160027690A1

公开(公告)日：2016-01-28

申请号：US14876640

申请日：2015-10-06

Applicant: ROHM CO., LTD.

Inventor： Yuichi NAKAO ,  Satoshi KAGEYAMA ,  Masaru NAITOU

IPC: H01L21/768

CPC classification number: H01L23/528 ,  B23D51/125 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/5329 ,  H01L24/05 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079

Abstract: The semiconductor device according to the present invention includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the first insulating layer, a second insulating layer laminated on the first insulating layer, a second metal wiring pattern embedded in a wire-forming region of the second insulating layer and first dummy metal patterns embedded each in a wire-opposed region opposing to the wire-forming region of the second insulating layer and in a non-wire-opposed region opposing to a non-wire-forming region other than the wire-forming region of the second insulating layer, the wire-opposed region and the non-wire-opposed region each in a non-wire-forming region other than the wire-forming region of the first insulating layer.

公开(公告)号：US20150054128A1

公开(公告)日：2015-02-26

申请号：US14516620

申请日：2014-10-17

Applicant: ROHM CO., LTD.

Inventor： Yuichi NAKAO

IPC: H01L27/115 ,  H01L49/02

CPC classification number: H01L27/11507 ,  H01L27/11502 ,  H01L28/55 ,  H01L28/57 ,  H01L28/60 ,  H01L28/65 ,  H01L28/75

Abstract: The semiconductor device according to the present invention includes a ferroelectric film and an electrode stacked on the ferroelectric film. The electrode has a multilayer structure of an electrode lower layer in contact with the ferroelectric film and an electrode upper layer stacked on the electrode lower layer. The electrode upper layer is made of a conductive material having an etching selection ratio with respect to the materials for the ferroelectric film and the electrode lower layer. The upper surface of the electrode upper layer is planarized.

公开(公告)号：US20140284731A1

公开(公告)日：2014-09-25

申请号：US14224489

申请日：2014-03-25

Applicant: ROHM CO., LTD.

Inventor： Yuichi NAKAO ,  Yasuhiro FUWA

IPC: H01L23/495

CPC classification number: B81B7/0074 ,  B81B2201/0235 ,  B81B2203/0315 ,  H01L23/13 ,  H01L23/147 ,  H01L23/24 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49579 ,  H01L23/49816 ,  H01L23/49827 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15156 ,  H01L2924/15165 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/157 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2224/81 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate that is made of a semiconductor material and has a main surface formed with a recess. The semiconductor device also includes a wiring layer formed on the substrate, an electronic element housed in the recess, and a sealing resin covering at least a part of the electronic element.

Abstract translation: 半导体器件包括由半导体材料制成并具有形成有凹部的主表面的衬底。 半导体器件还包括形成在基板上的布线层，容纳在凹部中的电子元件以及覆盖电子元件的至少一部分的密封树脂。

公开(公告)号：US20140045308A1

公开(公告)日：2014-02-13

申请号：US14054298

申请日：2013-10-15

Applicant: ROHM CO., LTD.

Inventor： Yuichi NAKAO

IPC: H01L29/66

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L21/76232 ,  H01L27/11521 ,  H01L29/42324

Abstract: A semiconductor storage device according to the present invention includes: a semiconductor substrate; an embedded insulator embedded in a trench formed in the semiconductor substrate and having an upper portion protruding above a top surface of the semiconductor substrate; a first insulating film formed on the top surface of the semiconductor substrate; a floating gate formed on the first insulating film at a side of the embedded insulator, having a side portion arching out above the embedded insulator, and having a side surface made of a flat surface and a curved surface continuing below the flat surface; a second insulating film contacting an upper surface, the flat surface and the curved surface of the floating gate; and a control gate opposing the upper surface, the flat surface and the curved surface of the floating gate across the second insulating film.

Abstract translation: 根据本发明的半导体存储装置包括：半导体衬底; 嵌入在所述半导体衬底中形成的沟槽中的嵌入式绝缘体，并具有突出在所述半导体衬底的顶表面上方的上部; 形成在所述半导体衬底的顶表面上的第一绝缘膜; 形成在所述嵌入式绝缘子的一侧上的所述第一绝缘膜上的浮动栅极，具有在所述嵌入绝缘体上方拱起的侧部，并且具有由平坦表面制成的侧表面和在所述平坦表面下方延伸的弯曲表面; 接触浮动栅极的上表面，平坦表面和曲面的第二绝缘膜; 以及控制门，其跨越第二绝缘膜与浮动栅极的上表面，平坦表面和弯曲表面相对。