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    FAN-OUT SEMICONDUCTOR PACKAGE
    15.
    发明申请
    FAN-OUT SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20190164926A1

    公开(公告)日：2019-05-30

    申请号：US16010754

    申请日：2018-06-18

    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

    Inventor： Yong Jin Seol ,  Myung Sam Kang ,  Young Gwan Ko

    IPC: H01L23/00 ,  H01L23/13 ,  H01L23/498 ,  H01L23/31

    Abstract: A fan-out semiconductor package includes a core member having a through-hole in which a semiconductor chip is disposed. The semiconductor chip has an active surface having connection pads disposed thereon and an inactive surface opposing the active surface. An encapsulant encapsulates at least a portion of the semiconductor chip. A connection member is disposed on the active surface of the semiconductor chip and includes a redistribution layer electrically connected to the connection pads of the semiconductor chip. A passivation layer is disposed on the connection member. The fan-out semiconductor package further has a slot spaced part from the through-hole and penetrating through at least a portion of the core member or the passivation layer.

    Circuit board and circuit board assembly
    16.
    发明授权
    Circuit board and circuit board assembly 有权

    公开(公告)号：US10212803B2

    公开(公告)日：2019-02-19

    申请号：US15198110

    申请日：2016-06-30

    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

    Inventor： Tae Hong Min ,  Myung Sam Kang ,  Jung Han Lee ,  Young Gwan Ko

    IPC: H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H05K3/46

    Abstract: A circuit board includes an insulating part including insulating layers, metal layers disposed on the insulating layers, vias each passing through at least one insulating layer among the insulating layers and connecting together at least two metal layers among the metal layers; a first thermally conductive structure including a thermally conductive material, at least a part of the thermally conductive structure being inserted into the insulating part, a first via having one surface contacting the first thermally conductive structure, a first metal pattern contacting another surface of the first via, a first bonding member connected to the first metal pattern, and pads to which a first electronic component is connected on an outermost surface of a metal layer disposed on an outermost surface of the insulating part, the pads being at least in a first region and a second region having a higher temperature than the first region.

    MULTILAYER TYPE CORELESS SUBSTRATE AND METHOD OF MANUFACTURING THE SAME
    20.
    发明申请
    MULTILAYER TYPE CORELESS SUBSTRATE AND METHOD OF MANUFACTURING THE SAME 审中-公开
    多层无机基材及其制造方法

    公开(公告)号：US20140027156A1

    公开(公告)日：2014-01-30

    申请号：US13664091

    申请日：2012-10-30

    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD

    Inventor： Ki Hwan Kim ,  Myung Sam Kang ,  Keung Jin Sohn ,  Yoong Oh ,  Da Hee Kim ,  Ki Young Yoo ,  Han Ui Lee ,  Sang Hyuck Oh

    IPC: H05K3/46 ,  H05K3/14 ,  H05K3/10 ,  H05K3/40 ,  H05K1/11 ,  H05K1/09

    CPC classification number: H05K3/4682 ,  H05K3/0097 ,  H05K3/4647 ,  H05K2203/0152 ,  H05K2203/1536 ,  Y10T29/49155 ,  Y10T29/49156

    Abstract: Disclosed herein is a method of manufacturing a multilayer type coreless substrate, the method including: (A) preparing a carrier substrate including at least one copper foil formed on one surface or both surfaces of an insulating surface; (B) forming a coreless printed circuit precursor on one surface or both surfaces of the carrier substrate; (C) separating the carrier substrate; (D) performing a polishing cutting process on the coreless printed circuit precursor; and (E) laminating a plurality of other insulating layers on a flat outer surface of the coreless printed circuit precursor, the plurality of other insulating layers sequentially including other circuit layers and other pillars.

    Abstract translation: 本发明公开了一种制造多层型无芯基板的方法，该方法包括：（A）制备载体基板，其包括在绝缘表面的一个表面或两个表面上形成的至少一个铜箔; （B）在载体基板的一个表面或两个表面上形成无芯无印刷电路前体; （C）分离载体基板; （D）对无芯印刷电路前体进行抛光切割处理; 以及（E）在所述无芯印刷电路前体的平坦外表面上层叠多个其它绝缘层，所述多个其它绝缘层依次包括其它电路层和其他柱。

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